Address Mapping Research Articles

TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices

NAND flash memory is widely used for the secondary storage of computer systems. The flash translation layer (FTL) is the firmware that manages and operates a flash-based storage device. One of the FTL's modules manages the RAM buffer of the flash device. Now this RAM buffer is sufficient to be used for both address mapping and data buffering. As the fastest component of the flash layer interface, effective management of this buffer has a significant impact on the performance of data storage and access. This paper proposes a novel scheme called TreeFTL for this purpose. TreeFTL organizes address translation pages and data storage pages in a tree-like structure in the RAM buffer. The tree enables TreeFTL to adapt to the access behaviors of workloads by dynamically adjusting the partitions for address mapping and data buffering. Furthermore, TreeFTL employs a lightweight mechanism to evict the least-recently-used victim pages when the need arises. Our experiments show that TreeFTL is able to spend 46.6 and 49.0 percent less service time over various workloads than two state-of-the-art algorithms, respectively, for a 64 MB RAM buffer.

Performance Evaluation of Dynamic Page Allocation Strategies in SSDs

Solid-state drives (SSDs) with tens of NAND flash chips and highly parallel architectures are widely used in enterprise and client storage systems. As any write operation in NAND flash is preceded by a slow erase operation, an out-of-place update mechanism is used to distribute writes through SSD storage space to postpone erase operations as far as possible. SSD controllers use a mapping table along with a specific allocation strategy to map logical host addresses to physical page addresses within storage space. The allocation strategy is further responsible for accelerating I/O operations through better striping of physical addresses over SSD parallel resources. Proposals already exist for using static logical-to-physical address mapping that does not balance the I/O traffic load within the SSD, and its efficiency highly depends on access patterns. A more balanced distribution of I/O operations is to alternate resource allocation in a round-robin manner irrespective of logical addresses. The number of resources that can be dynamically allocated in this fashion is defined as the degree of freedom, and to the best of our knowledge, there has been no research thus far to show what happens if different degrees of freedom are used in allocation strategy. This article explores the possibility of using dynamic resource allocation and identifies key design opportunities that it presents to improve SSD performance. Specifically, using steady-state analysis of SSDs, we show that dynamism helps to mitigate performance and endurance overheads of garbage collection. Our steady-state experiments indicate that midrange/high-end SSDs with dynamic allocation can provide I/O operations per second (IOPS) improvement of up to 3.3x/9.6x, response time improvement of up to 56%/32%, and about 88%/96% average reduction in the standard deviation of erase counts of NAND flash blocks.

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Multicore processors have proliferated several domains ranging from small-scale embedded systems to large data centers, making tiled CMPs (TCMPs) the essential next-generation scalable architecture. NUCA architectures help in managing the capacity and access time for such larger cache designs. It divides the last-level cache (LLC) into multiple banks connected through an on-chip network. Static NUCA (SNUCA) has a fixed address mapping policy, whereas dynamic NUCA (DNUCA) allows blocks to relocate nearer to the processing cores at runtime. To allow this, DNUCA divides the banks into multiple banksets and a block can be placed in any bank within a particular bankset. The entire bankset may need to be searched to access a block. Optimal bankset searching mechanisms are essential for getting the benefits from DNUCA. This article proposes a DNUCA-based TCMP architecture called TLD-NUCA. It reduces the LLC access time of TCMP and also allows a heavily loaded bank to distribute its load among the underused banks. Instead of other DNUCA designs, TLD-NUCA considers larger banksets. Such relaxations result in more uniform load distribution than existing DNUCA-based TCMP (T-DNUCA). Considering larger banksets improves the utilization factor, but T-DNUCA cannot implement it because of its expensive searching mechanism. TLD-NUCA uses a centralized directory, called TLD, to search a block from all the banks. Also, the proposed block placement policy reduces the instances when the central TLD needs to be contacted. It does not require the expensive simultaneous search as needed by T-DNUCA. Better cache utilization and a reduction in LLC access time improve the miss rate as well as the average memory access time (AMAT). Improving the miss rate and AMAT results in improvements in cycles per instructions (CPI). Experimental analysis found that TLD-NUCA improves performance by 6.5% as compared to T-DNUCA. The improvement is 13% as compared to the SNUCA-based TCMP design.

Protocol Verification of Translation in Mobile Internet Protocol Version 4 and 6

Verifying a protocol means ensuring that it is free of logical errors prior to implementing it. The goal of verifying the protocol is to guarantee that protocol does exactly what the designer intended. This paper presents the methodology to verify protocols in transition phase of Mobile IP. Due to insufficient addresses in IPv4 there is an urgent need to switch to IPv6. Translation is an effective technique that enables IPv4-only devices to communicate with IPv6-only devices. This paper deals with operation of Address translation & Mapping technique in Translation. The Design Analysis in this paper demonstrates methodology to verify translation of IPv4 data packet to IPv6 data packet.

Capacity-Independent Address Mapping for Flash Storage Devices with Explosively Growing Capacity

Address mapping for flash storage devices has been a challenging design issue for controllers because of rapidly growing device capacity. In contrast with existing mapping methods, this study proposes a capacity-independent address mapping method to decouple the required on-device RAM space from the capacity of a flash storage device. Especially, the required RAM size of the proposed method depends only on the user accessed data set, which is also referred to as the working set, while the page-level performance can be nearly achieved. In addition, a simple but practical wear-leveling design is proposed with the capability in lifetime estimation of flash storage devices. Experiments of the proposed scheme obtained encouraging results.

A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage Devices

Current triple-level cell (TLC)-based solids-tate drives used in multimedia storage devices support multichannel access to increase capacity and throughput. Unfortunately, current state-of-the-art FTL algorithms must employ selective caching for inquiring about the address mapping information, which causes low space utilization, a large flash memory requirement, and performance degradation. In this article, the <u>Ca</u> che- <u>b</u> ased Flash Translation Layer (Cab-FTL) is proposed for TLC-based multimedia storage devices. Cab-FTL enhances the read and write performances by achieving high space utilization while reducing the size of the mapping tables to 1.68% compared to DFTL. Despite a caching of the mapping tables in DRAM, Cab-FTL achieves a fast system boot using its fast wake-up mechanism.

A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems

NAND flash memory is widely used in both hard real-time and soft real-time systems because of its unique properties, such as non-volatility, low power consumption, and fast access time. However, due to the variable garbage collection latency, the response time becomes unpredictable when multiple I/O requests are issued from the file system to flash media. In NAND flash memory storage systems, flash translation layer (FTL) is a typical software module to handle the I/O requests and manage NAND flash memory. Most of existing FTL schemes focus on improving average response time but worst-case response time remains an open problem. This paper proposes a real-time flash translation layer (RFTL) scheme to evenly distribute garbage collection time-cost, so as to guarantee a near optimum worst-case response time. This is achieved by using a new hybrid-level address mapping approach, which can provide guaranteed physical space to serve requests in any time period. Moreover, we propose a distributed garbage collection policy that enables RFTL to reclaim the space and serve the requests simultaneously. We conduct a set of experiments on a real hardware platform. Both the proposed scheme and other representative FTL schemes have been implemented in the hardware evaluation board. Experimental results show that our scheme improves worst-case response time by 41.51 percent and average response time by 88.85 percent.

Review of Security Research on Address Resolution Protocols

Address resolution protocols (ARPs includes ARP, NDP, SEND, etc.) play an important role in network communication; the security of the ARPs is the premise and guarantee of network security. ARPs consists of three phases: acquisition of the mapping of the target address; duplicate address detection; data structure maintenance. In this paper, we analyze the existing ARPs according to these three phases, analyze security threats and the corresponding attack methods; classify and describe the existing studies on ARPs security. Our analysis shows that the main factors that restrict the development of ARPs are the contradiction between efficiency and cost and the lack of theoretical support in protocol design. Finally, the development of ARPs is prospected.

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high performance, supporting the PGAS memory model is associated with penalties that can hinder PGAS’s potential for scalability and speed of execution. This is because mapping the PGAS memory model to the underlying system requires a mapping process that is done in software, thereby introducing substantial overhead for shared accesses even when they are local. Compiler optimizations have not been sufficient to offset this overhead. On the other hand, manual code optimizations can help, but this eliminates the productivity edge of PGAS. This article proposes a processor microarchitecture extension that can perform such address mapping in hardware with nearly no performance overhead. These extensions are then availed to compilers through extensions to the processor instructions. Thus, the need for manual optimizations is eliminated and the productivity of PGAS languages is unleashed. Using Unified Parallel C (UPC), a PGAS language, we present a case study of a prototype compiler and architecture support. Two different implementations of the system were realized. The first uses a full-system simulator, gem5, which evaluates the overall performance gain of the new hardware support. The second uses an FPGA Leon3 soft-core processor to verify implementation feasibility and to parameterize the cost of the new hardware. The new instructions show promising results on all tested codes, including the NAS Parallel Benchmark kernels in UPC. Performance improvements of up to 5.5× for unmodified codes, sometimes surpassing hand-optimized performance, were demonstrated. We also show that our four-core FPGA prototype requires less than 2.4% of the overall chip’s area.

Research and Implementation on Virtual Network Mapping Mechanism based on SDN

Network virtualization technology allows multiple logical networks or network applications to run simultane- ously on the underlying physical network. The virtual network mapping is the key method to realize network virtualiza- tion. Virtual tenant network (VTN) is a new technique for construction of multi-tenant network in software definition networking (SDN) network. VTN mapping mechanism is a core problem. In this paper MAC address-based mapping method which maps the host to the virtual network according to the host's MAC address is proposed. Besides, a virtual network based on MAC address mapping method is established to verify the effectiveness of the VTN mapping method based on MAC address.

Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations

Phase change memory (PCM) has a write endurance problem. This problem is exacerbated due to endurance variations (EVs) when using advanced process technology (e.g., sub-20 nm), where PCM is expected to provide scaling benefits over dynamic random access memory (RAM). Wear leveling can solve this problem by dynamically changing the mapping from memory addresses to PCM physical addresses such that all PCM cells are evenly written, thereby extending the effective lifetime of such devices. PCM permits fine-grained writes, i.e., even bit level updates are allowed. To allow fine-grained wear leveling, this capability must be exploited. However, previous wear leveling approaches do not fully exploit fine-grained writes since fine-grained writes cause them to suffer from high data copy (called swap) overhead for address remapping, and/or high area and runtime overhead for the management of write frequency and address mapping information. This paper proposes a dynamic wear leveling method for PCMs that addresses all of these issues. The method: 1) uses bloom filters to enable low-cost write counters for fine-grained writes and 2) exploits the EV of PCM cells to avoid mapping hot data onto weak cells. To improve the effectiveness of the bloom filters, dynamic bloom filter management (write counts, hash functions, and write counter thresholds) and hot-cold address lists are used. The proposed method was evaluated using simulations and a hardware implementation. Using a small amount of PCM capacity overhead (0.3%), the proposed method extended the lifetime of a PCM device by 2.8–4.6 times over the existing methods when there were significant EVs.

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

In embedded systems, especially battery-driven mobile devices, energy is one of the most critical performance metrics. Due to its high density and low standby power, phase change memory (PCM), an emerging non-volatile memory device, is becoming a promising dynamic random access memory (DRAM) alternative. Recent studies have proposed the hybrid main memory architecture integrating both PCM and DRAM to fully take advantage of the properties of both memories. However, the low power performance of PCM in the hybrid main memory architecture has not been fully explored. Therefore, it becomes an interesting problem to utilize PCM and DRAM as hybrid main memory for energy optimization in embedded systems. In this paper, we present an energy optimization technique for hybrid main memory architecture. The objective is to fully utilize PCM to reduce the energy consumption while ensuring that the real-time performance of applications are guaranteed. We propose a two-phase approach to solve hybrid main memory address mapping problem. In the first phase, we calculate energy and time cost for each address based on the task models. Then the applications can be modeled as data-flow graph nodes, and different access times will associate with different energy consumption. In the second phase, for different memory types and the given timing constraint, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal solution. The ILP model can map a proper memory type for each address such that the total energy consumption can be minimized while the timing constraint is satisfied. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on an ARM-based simulator. The experimental results show that our method can effectively reduce the energy consumption with the least system cost compared with the previous work.

LTE turbo decoder design**Project supported by the LTE-Advanced User Equipment Software Baseband Technology Major Project of China (No. 2013ZX0300315001).

This paper presents a turbo decoder supporting all 188 block sizes in 3GPP long term evolution (LTE) standard which can be employed in the LTE micro-eNodB system. The design allows 1, 2, 4, 8 or 16 soft-in/soft-out (SISO) decoders to concurrently process each block size, and the number of iterations can be adjusted. By adding a register in core structure add-compare-select-add, this article proposes an improved SISO algorithm and interleaving design, calculated forward state matrix and backward state matrix alternately, and the branch transition probability can be used in the Turbo decode process directly just after one clock delay. The structure enables a decoder processing radix-2 algorithm with high speed, instead of radix-4 as the conventional decoder. Moreover, the paper details an interleaver/de-interleaver, which is combined by two operational steps. One is column address mapping and the other is intra-row permutation. Decoder realizes interleaving by loading data from memories whose address is generated by column mapping and then lets data passing through inter-row permutation. For de-interleaving, the system can adopt reverse operation.

Lazy-RTGC

Due to many attractive and unique properties, NAND flash memory has been widely adopted in mission-critical hard real-time systems and some soft real-time systems. However, the nondeterministic garbage collection operation in NAND flash memory makes it difficult to predict the system response time of each data request. This article presents Lazy-RTGC , a real-time lazy garbage collection mechanism for NAND flash memory storage systems. Lazy-RTGC adopts two design optimization techniques: on-demand page-level address mappings, and partial garbage collection. On-demand page-level address mappings can achieve high performance of address translation and can effectively manage the flash space with the minimum RAM cost. On the other hand, partial garbage collection can provide the guaranteed system response time. By adopting these techniques, Lazy-RTGC jointly optimizes both the average and the worst system response time, and provides a lower bound of reclaimed free space. Lazy-RTGC is implemented in FlashSim and compared with representative real-time NAND flash memory management schemes. Experimental results show that our technique can significantly improve both the average and worst system performance with very low extra flash-space requirements.

A fully associative, tagless DRAM cache

This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of virtual-to-physical, address mappings. At a TLB miss, the TLB miss handler allocates the requested block into the cache if it is not cached yet, and updates both the page table and cTLB with the virtual-to-cache address mapping. Assuming the availability of large in-package DRAM caches, this ensures that an access to the memory region within the TLB reach always hits in the cache with low hit latency since a TLB access immediately returns the exact location of the requested block in the cache, hence saving a tag-checking operation. The remaining cache space is used as victim cache for memory pages that are recently evicted from cTLB. By completely eliminating data structures for cache tag management, from either on-die SRAM or in-package DRAM, the proposed DRAM cache achieves best scalability and hit latency, while maintaining high hit rate of a fully associative cache. Our evaluation with 3D Through-Silicon Via (TSV)-based in-package DRAM demonstrates that the proposed cache improves the IPC and energy efficiency by 30.9% and 39.5%, respectively, compared to the baseline with no DRAM cache. These numbers translate to 4.3% and 23.8% improvements over an impractical SRAM-tag cache requiring megabytes of on-die SRAM storage, due to low hit latency and zero energy waste for cache tags.

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2n-input network can be configured to support any 2i-input (0≤i≤n) network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130nm CMOS technology, the design achieves 384.3Mbps peak throughput at clock rate of 290MHz with 5.5 iterations. Consuming 4.02mm2 core area and 716mW power, the decoder has a 1.81bits/cycle/iteration/mm2 architecture efficiency and a 0.34nJ/bit/iteration energy efficiency, which is competitive with other recent works.

NAND 플래시 메모리 기반 B+ 트리에서 페이지 매핑 로그를 이용한 색인 관리 기법

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in -Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

Design and Optimization of Hierarchical Routing Protocol for 6LoWPAN

To build scalable and lightweight wireless sensor networks with energy saving devices, 6LoWPAN-based protocols become emergent technologies that successfully constructed ubiquitous networks and seamlessly connected the traditional Internet with WSNs. However, the existing researches cannot effectively maintain the routing and the network topology for the problems of low cost sensors' malfunctions. In this paper, we improved the HiLow protocol in aspects of interconnection between the Internet and 6LoWPAN and designed a network routing path recovery approach. In addition, we designed and modified the address mapping table in gateway to store and map nodes' EUI-64 address and 16-bit short address. Nodes from the Internet can access the 6LoWPAN nodes by an IPv6 address, which is generated by the EUI-64 address and IPv6 prefix. Due to the benefits of additional data structure and our designs, the simulation results manifested that our protocol improves the routing efficiency and can effectively reduce the cost for network reorganization caused by node failures and mobiles.

NDPA: A generalized efficient parallel in-place N-Dimensional Permutation Algorithm

N-dimensional transpose/permutation is a very important operation in many large-scale data intensive and scientific applications. These applications include but not limited to oil industry i.e. seismic data processing, nuclear medicine, media production, digital signal processing and business intelligence. This paper proposes an efficient in-place N-dimensional permutation algorithm. The algorithm is based on a novel 3D transpose algorithm that was published recently. The proposed algorithm has been tested on 3D, 4D, 5D, 6D and 7D data sets as a proof of concept. This is the first contribution which is breaking the dimensions’ limitation of the base algorithm. The suggested algorithm exploits the idea of mixing both logical and physical permutations together. In the logical permutation, the address map is transposed for each data unit access. In the physical permutation, actual data elements are swapped. Both permutation levels exploit the fast on-chip memory bandwidth by transferring large amount of data and allowing for fine-grain SIMD (Single Instruction, Multiple Data) operations. Thus, the performance is improved as evident from the experimental results section. The algorithm is implemented on NVidia GeForce GTS 250 GPU (Graphics Processing Unit) containing 128 cores. The rapid increase in GPUs performance coupled with the recent and continuous improvements in its programmability proved that GPUs are the right choice for computationally demanding tasks. The use of GPUs is the second contribution which reflects how strongly they fit for high performance tasks. The third contribution is improving the proposed algorithm performance to its peak as discussed in the results section.

COUNTING BLOOM FILTER ARCHITECTURE IN VLSI NETWORK SYSTEMS

The Counting Bloom Filter (CBF) is useful for real time applications where the time and space efficiency is the main consideration in performing a set membership tests. The CBF estimates whether an element is present in a large array or not by allowing false positives and by not permitting false negatives. In this paper CBF architecture is analyzed and has been implemented. There are two approaches of CBF, SRAM based approach using up/down counters and the LCBF using up/down LFSR unit. In this paper the LCBF architecture discussed and analyzed. In the latest VLSI technology it is easy to fabricate memories that hold a few million bits of data and addresses. But in the recent embedded memory technologies rather than mapping of addresses of 5000 bits of data using hashing functions we can concise in to single contiguous memory.