Additional Transistors Research Articles

Design and analysis of SRAM cell using swing restoration inverter for low power applications

ABSTRACT SRAM cells play a crucial role in the design of system-on-chips (SoCs), constituting a substantial portion of the die area and thereby contributing to increased power consumption. Despite significant advancements in SRAM performance in finer technologies, concerns persist regarding cell stability in the deep sub-micron domain. This article introduces an innovative approach to address these issues by proposing a low-power SRAM cell based on Swing Restoration Inverter (SRI). The Swing Restoration Inverter (SRI) addresses the challenge of swing voltages in finer technologies by integrating two additional transistors to act as swing-restored elements. This innovation results in an impressive 67% reduction in leakage power at 27°C for the 90 nm technology. To evaluate the effectiveness of the proposed SRI-based SRAM cell, performance metrics such as delay and power delay product are calculated. In the context of a 6T SRAM cell in the 90 nm technology, the conventional inverters are replaced with the Swing Restoration Inverter (SRI). The implementation of SRI in an 8T SRAM cell leads to a substantial 91% reduction in leakage power at 30°C and an impressive 93% reduction at 27°C compared to the conventional 6T SRAM cell. The SRI technique proves instrumental in enhancing stability, resulting in the proposed 8T SRAM cell outperforming its 6T SRAM counterpart. However, it’s important to note that the heightened performance of the proposed 8T SRAM cell comes at the expense of four additional transistors. Simulations are conducted using the 90 nm technology and the Cadence Virtuoso simulator to validate the effectiveness of the Swing Restoration Inverter (SRI) technique in mitigating power consumption and enhancing stability in SRAM cells.

A SET‐tolerant StrongARM comparator with improved performance

AbstractIn this paper, a radiation hardened by design StrongARM comparator is proposed to mitigate the radiation effects. With 12 additional transistors compared to the conventional one, the proposed structure shows much higher immunity to single‐event transients. During the amplification phase, when the input differential voltage is 10 mV, the proposed structure can withstand up to 18fC free charge, 45x far surpassing the conventional structure. During the regeneration phase, every sensitive node in the proposed structure can withstand a 200 fC‐injected charge. Compared to other redundant structures with performance deterioration, the proposed architecture exhibits high‐speed characteristics. When the differential voltage between two inputs is 1 mV, the delay of the new structure is 168.26 ps and the speed improvement is 118.02% over the conventional structure.

Compensated Current Mirror Neuron Circuits for Linear Charge Integration with Ultralow Static Power in Spiking Neural Networks

For energy‐ and time‐efficient artificial intelligence (AI) computing, implementing hardware‐based spiking neural networks (SNNs) has become a core technology. In SNNs, synaptic devices store weights in memory, and neurons process received weighted information and generate spike signals. Upon feeding spike signals into synaptic arrays, the synaptic weights multiply the signals, which subsequently sum up to perform vector‐matrix multiplication (VMM). Simultaneous access to multiple synaptic devices, however, reduces the equivalent resistance of these synaptic arrays. This reduction alters the voltage division between the pre‐synaptic array and the input resistance of the neuron circuit, distorting the read voltage across synaptic devices. This phenomenon is known as the fan‐in problem, which leads to non‐ideal VMM operations and degrades system accuracy. To address this issue, a novel compensated current mirror (CCM) neuron circuit is proposed, which incorporates a single additional transistor into a conventional current mirror. This CCM neuron achieves exceptional current linearity (R2 > 0.999) and efficiently compensates for VMM error with low complexity and energy consumption (3.33 pJ spike−1). Furthermore, the CCM neuron demonstrates ≈7‐%p higher inference accuracy than conventional ones when integrated with a 512 × 512 large‐scale synaptic array, which is comparable to the accuracy of software‐based SNNs.

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University’s 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency.

A 2.41 ppm/°C bandgap voltage reference with second‐order curvature compensation

SummaryA current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV.

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

AbstractStatic random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

Investigation of the Global Shutter Operation of the Quantum-Dot Short-Wave Infrared Image Sensor

Quantum dot (QD) thin-film photodiodes (TFPDs) are studied extensively in the image sensor field as they can pave the way toward the cost-efficient implementation of short-wave infrared (SWIR) cameras. Interestingly, the QD TFPD image sensors can be operated in the global shutter (GS) mode by turning on the photodiode (PD) only during integration time and subsequently turning it off during the readout. This offers the substantial advantage of reducing the pixel size as it eliminates the need for additional transistors or capacitors that are otherwise typically used in conventional GS pixels. So far, no comprehensive study has yet been performed on this PD turn on/off operation mode. Therefore, in this work, we investigated the PD turn on/off GS operation mode in comparison with the conventional voltage domain (VD) GS operation—a first in-depth report of its kind. We confirm that the PD turn on/off GS mode has the advantage of a small pixel size but comes at the cost of an increasing nonlinearity as the integration time approaches the PD speed limitation. We report a parasitic light sensitivity (PLS) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 70 dB over the visible (VIS) and SWIR range and moreover demonstrate that the PLS has the potential to reach <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 100 dB based on the discrete PD measurement.

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

SummaryThis paper demonstrates an ultra‐efficient, fully programmable membership function generator (MFG) utilizing independent double‐gate (IDG) FinFET technology. The proposed MFG can produce s‐shaped, z‐shaped, triangular, and trapezoidal membership functions. By employing only six transistors, the designed MFG provides full controllability over the height, position, width, and slope of the generated waveforms. Without using any additional transistor and changing the dimensions, the proposed MFG can calibrate the slope of the output based on the back‐gate bias voltage of the IDG‐FinFETs. According to our extensive simulations, the proposed MFG shows promising improvements in transistor count (70%), power‐delay‐product (PDP) (80%), and maximum absolute error (61%) as compared with its state‐of‐the‐art counterparts. To benchmark the functionality of the proposed MFG in practical applications, our generated membership function is exploited as the neuron's activation function in a multilayer perceptron (MLP) neural network. The simulation results indicate that the training process of the simulated MLP with the proposed MFG closely tracks the results obtained from the ideal MLP with the sigmoid activation function. A figure of merit (FoM) is defined considering the hardware efficiency and accuracy of the neural networks to evaluate the entire performance of the proposed MFG. The FoM simulations demonstrate that the proposed MFG presents an excellent trade‐off between hardware performance and accuracy in neural network applications. Our results emphasize that the proposed MFG is a potential candidate for designing high‐performance on‐chip neural networks.

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

This article presents a programmable in-memory computing accelerator (PIMCA) for low-precision (1–2 b) deep neural network (DNN) inference. The custom 10T1C bitcell in the in-memory computing (IMC) macro has four additional transistors and one capacitor to perform capacitive-coupling-based multiply and accumulation (MAC) in analog-mixed-signal (AMS) domain. A macro containing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256\ttimes 128$</tex-math> </inline-formula> bitcells can simultaneously activate all the rows, and as a result, it can perform a matrix-vector multiplication (VMM) in one cycle. PIMCA integrates 108 of such IMC static random-access memory (SRAM) macros with the custom six-stage pipeline and the custom instruction set architecture (ISA) for instruction-level programmability. The results of IMC macros are fed to a single-instruction-multiple-data (SIMD) processor for other computations such as partial sum accumulation, max-pooling, activation functions, etc. To effectively use the IMC and SIMD datapath, we customize the ISA especially by adding hardware loop support, which reduces the program size by up to 73%. The accelerator is prototyped in a 28-nm technology, and integrates a total of 3.4-Mb IMC SRAM and 1.5-Mb off-the-shelf activation SRAM, demonstrating one of the largest IMC accelerators to date. It achieves the system-level energy efficiency of 437 TOPS/W and the peak throughput of 49 TOPS at the 42-MHz clock frequency and 1-V supply for the VGG9 and the ResNet-18 on the CIFAR-10 dataset.

High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM.

Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%.

On-Chip Dynamic Gate-Voltage Waveform Sampling in a 200-V GaN-on-SOI Power IC

The continual improvement of GaN-on-Si processes motivates the integration of more complex circuits alongside GaN power devices. Additional transistors can be leveraged to provide control, logic, and protection; however, low-voltage GaN devices consume more power and area than similar CMOS counterparts. This article investigates the feasibility of a monolithic gate-monitoring circuit integrated with a GaN power device and gate driver. The monitoring circuit captures 16 samples within 50 ns during the gate rising transient and stores them in on-chip capacitors. The stored voltages are asynchronously read off-chip through integrated source-follower buffers and a digitally controlled multiplexer. The proposed design incorporates approximately 330 e-HEMT transistors and was fabricated in a 200-V GaN-on-SOI process. A detailed characterization was performed to calibrate the dynamic on-chip gate voltage from the sampled values that are read off-chip, paving the way for future active control based on this feedback. Experimental results and the postcalibration estimate of the on-chip gate voltage highlight that off-chip measurements are poor and pessimistic estimators for the on-chip dynamic excursions. The on-chip gate-voltage waveform was estimated using the sampling circuit while switching the power device at 80 V, 1.5 A, demonstrating more accurate measurements of on-chip signals. This circuit stands as a proof-of-concept for the viability of integrating relatively complex circuits in GaN power ICs to perform critical monitoring and sensing tasks.

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance.

A 7T SECURITY ORIENTED SRAM BITCELL USING VLSI

Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor (6T) static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel power analysis attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000× lower write energy standard deviation between write ‘1’ and ‘0’ operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other power analysis resistant SRAM cells. Key Words: Power Analysis, SRAM Design, 6T SRAM, 7T SRAM, Power Dissipation Software Tools:  Tanner eda Tool

Ultra-Efficient and Robust Auto-Nonvolatile Schmitt Trigger-Based Latch Design Using Ferroelectric CNTFET Technology.

In designing ultra-efficient noise immune nanoscale circuits and systems, Schmitt triggers (STs) are vital components influencing total functionality. This article proposes an ultracompact ST using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs) and a robust ST latch. By using the unique electrical futures of the Fe-CNTFETs, the proposed ST has been designed in a particular way to only employ two transistors similar to a conventional binary inverter. Moreover, by utilizing the negative capacitance feature of the Fe-CNTFETs, the proposed ST can perform the backup and restore operation during a scheduled power gating or a sudden power outage without imposing any additional transistors, interconnects, and control signals. The proposed ST latch is hardened to soft errors occurring due to unwanted single-event upsets (SEUs). Our extensive simulations demonstrate that our proposed ST latch offers lower transistors counts (on average 34%) and more energy savings (on average 79%). On the other hand, our design has shown 5.6 times on average higher critical charge tolerance than the previous counterparts due to its soft error hardening circuity and the superior hysteresis behavior of the proposed Fe-CNTFET-based ST. Moreover, the auto-nonvolatility of the proposed ST makes the proposed latches immune to the sudden power outage, which was not devised in the previous ST latches. Our results show new pathways in designing ultracompact and efficient nonvolatile ST latches using the Fe-CNTFET technology.

A 0.3 THz VCO using gm‐enhanced technology in 55 nm CMOS

AbstractA power combined terahertz (THz) voltage‐controlled oscillator (VCO) is proposed to increase the output power. Based on the traditional transformer‐feedback structure, a new negative conductance enhanced (gm‐enhanced) technology is presented to enhance the start‐up of the proposed THz VCO by adding additional transistors to offset the loss of the source inductance. In addition, a short transmission line is used as a zero‐phase shifter to lock the three single‐core VCOs for consistent frequency, phase, and amplitude. The fully integrated 300 GHz VCO design is fabricated in 55‐nm complementary metal oxide semiconductor (CMOS) process. The measurement results show that by modulating the bias voltage of the transistors, the VCO can achieve a tuning range of 301.2–304.2 GHz with a maximum output power of −7.5 dBm. The chip area is only 554 μm × 530 μm.

A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise.

Inductor-capacitor voltage controlled oscillators (LC-VCOs) are the most common type of oscillator used in sensors systems, such as transceivers for wireless sensor networks (WSNs), VCO-based reading circuits, VCO-based radar sensors, etc. This work presents a technique to reduce the LC-VCOs phase noise using a new current-shaping method based on a feedback injection mechanism with only two additional transistors. This technique consists of keeping the negative resistance seen from LC tank constant throughout the oscillation cycle, achieving a significant phase noise reduction with a very low area increase. To test this method an LC-VCO was designed, fabricated and measured on a wafer using 90 nm CMOS technology with 1.2 V supply voltage. The oscillator outputs were buffered using source followers to provide additional isolation from load variations and to boost the output power. The tank was tuned to 1.8 GHz, comprising two 1.15 nH with 1.5 turns inductors with a quality factor (Q) of 14, a 3.27 pF metal-oxide-metal capacitor, and two varactors. The measured phase noise was −112 dBc/Hz at 1 MHz offset. Including the pads, the chip area is 750 × 850 m.

An area and energy efficient LIF neuron model with spike frequency adaptation mechanism

As neuron is the fundamental unit of the nervous system, it is one of the main building blocks in the spiking neural networks hardware implementation. To implement hardware that consists of many thousands of neurons and accurately mimics the brain functions, an energy and area-efficient design for the neuron is essential. In this paper, we propose a VLSI circuit for the leaky integrate and fire (LIF) neuron model, in 130 nm CMOS technology. The proposed neuron has some important features: first, it consumes very low energy; second, it is simple and area-efficient. Third, it has the spike frequency adaptation capability that makes it more biologically plausible. The spike frequency adaptation mechanism is added to the model only by one additional transistor, and it is done just by one parameter. The energy per spike of the neuron circuit in the worst case is only 0.67 fJ/spike. The spike frequency is in the MHz range, which enables attractive hardware acceleration.

A Low Dark Current 160 dB Logarithmic Pixel with Low Voltage Photodiode Biasing

Extending CMOS Image Sensors’ dynamic range is of fundamental importance in applications, such as automotive, scientific, or X-ray, where a broad variation of incoming light should be measured. The typical logarithmic pixels suffer from poor performance under low light conditions due to a leakage current, usually referred to as the dark current. In this paper, we propose a logarithmic pixel design capable of reducing the dark current through low-voltage photodiode biasing, without introducing any process modifications. The proposed pixel combines a high dynamic range with a significant improvement in the dark response compared to a standard logarithmic pixel. The reported experimental results show this architecture to achieve an almost 35 dB improvement at the expense of three additional transistors, thereby achieving an unprecedented dynamic range higher than 160 dB.

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy of the data movements. However, due to the additional transistors, the CiM SRAMs suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile, monolithic 3D (M3D) integration enables fine-grained 3D integration, reducing the 2D wire length in small functional units. In this paper, we propose a BNN accelerator (BNN_Accel), composed of a 9T CiM SRAM (CiM_SRAM), input buffer, and global periphery logic, to execute the computations in the binarized convolution layers of BNNs. We also propose CiM_SRAM with the subarray-level M3D integration (as well as the transistor-level M3D integration), which reduces the wire latency and energy compared to the 2D planar CiM_SRAM. Across the binarized convolution layers, our simulation results show that BNN_Accel with the 4-layer CiM_SRAM reduces the average execution time and energy by 39.9% and 23.2%, respectively, compared to BNN_Accel with the 2D planar CiM_SRAM.