An area and energy efficient LIF neuron model with spike frequency adaptation mechanism

Abstract

As neuron is the fundamental unit of the nervous system, it is one of the main building blocks in the spiking neural networks hardware implementation. To implement hardware that consists of many thousands of neurons and accurately mimics the brain functions, an energy and area-efficient design for the neuron is essential. In this paper, we propose a VLSI circuit for the leaky integrate and fire (LIF) neuron model, in 130 nm CMOS technology. The proposed neuron has some important features: first, it consumes very low energy; second, it is simple and area-efficient. Third, it has the spike frequency adaptation capability that makes it more biologically plausible. The spike frequency adaptation mechanism is added to the model only by one additional transistor, and it is done just by one parameter. The energy per spike of the neuron circuit in the worst case is only 0.67 fJ/spike. The spike frequency is in the MHz range, which enables attractive hardware acceleration.