Addition Of Partial Products Research Articles

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

Design of Wallace tree multiplier circuit using high performance and low power full adder

The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.

A Fast (7, 3)-adder Circuit for High-speed Multiplier Design

A set of fast (m, 3)-adder circuits (4 ≤ m ≤ 7) is presented in this paper. An (m, 3)-adder adds m bits at a time and produces three outputs (N, C, S). These adders are designed to implement high-speed (7, 3)-adder based multipliers that use a (7, 3)-adder as a basic unit and five other adders ((6, 3), (5, 3), (4, 3), (3, 2), and (2, 2)-adder) as auxiliary units for the addition of partial products. Multipliers require adding tens of partial products to obtain a result, and they can be added by (7, 3)-adders more quickly than by (3, 2)-adders. In simulation results, the worst-case delay and power of the new (7, 3)-adder are 1.45 times and 2.4 times larger than those of the reference (3, 2)-adder. However, the parallel addition of partial products with the (7, 3)-adder is faster and consumes less power than with the (3, 2)-adder because the (7, 3)-adder based multiplier requires fewer adders and addition stages than a (3, 2)-adder based multiplier. This result shows that the speed of a multiplier can be increased by using (7, 3)-adders instead of (3, 2)-adders in reducing partial products.

VLSI implementation of booth multiplier and carry select adder based fir filter design for ECG signal denoising

Over the last two decades, FIR filters have been the subject of intense research. The design of an adder, which is a major building component in circuit design, determines the overall performance of a system. The Finite Impulse Response (FIR) filter has been increasingly popular in signal processing applications in recent years. For signal processing field applications and VLSI systems, many adders are implemented. Signal denoising, as well as the production of an effective multiplier, had never been explained in any of the previous publications. This paper proposes 8 bit booth multipliers for partial products. The design employs the Carry select and Booth techniques. For partial product addition, the Carry Select Adder (CSA) is employed. The architecture of the FIR filter is proposed for operation with Electro Cardiogram (ECG) signal. It's known as CSA-BOOTH FIR, and it's used for denoising. Using the MATLAB application, the ECG signal with noise is sent into the filter. The denoising method is written in Verilog, with the output recorded in a text file. The binary values are read in MATLAB to denoise the signal. The performance of FPGAs and ASICs is evaluated.

A Novel Design of High-Performance Hybrid Multiplier

In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.

16x16-Bit Binary Multiplier Using High-Speed Modified Compressor

Background: For higher-order multiplications, a huge number of adders or compressors are used to perform the addition of the partial products. Objective: Hence, the area and the propagation delay will increase. Researchers are trying to reduce the number of additions of partial products. Method: In this paper, different modified compressors have been proposed and based on these compressors, 16x16-bit binary multiplier has been discussed. Results: The proposed design provides better area, power consumption, critical path delay and less number of transistor counts when compared to other designs using the conventional compressors. Here, the proposed method has been used in the Wallace tree multiplier or Dadda tree multiplier. The compressor used here has been implemented using Microwind DSCH 3.8 lite. Conclusion: The modified compressor makes the multiplier faster and reduces the number of addition of partial products.

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for DSP systems. The eminent parallel and sequential multiplication algorithms include Shift and Add, Wallace Tree, Booth, and Array. The multiplier optimization attempts have also been reported in adders used for partial product addition. In this paper, analogous to conventional multipliers, two new multiplication algorithms implemented on FPGA are shown and compared with conventional algorithms as stand-alone and by using them in the implementation of FIR filters and adaptive channel equalizer using the LMS algorithm. The work is carried out on Spartan-6 FPG that may be extended for any type of FPGA. Results are compared in terms of resource utilization, power consumption, and maximum achieved frequency. The results show that for a small length of coefficients like 3-bit, the proposed algorithms work very well in terms of achieved frequency, consumed power, and even resource utilization. Whilst for the length greater than 3-bit, the Pipelined multiplier is much better in frequency than the proposed and conventional ones, and the Booth multiplier consumes fewer resources in terms of lookup tables.

Vedic-Based Squarers with High Performance

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24- bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12- bit, and 24- bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24- bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

Vedic-Based Squarers with High Performance

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24- bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12- bit, and 24- bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24- bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture

This paper presents the implementation and performance comparison of the Booth encoding technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth encoder is widely used to enhance the multiplication speed as it has the capability to reduce the number of partial products generated by half. Vedic multiplier partitions the inputs into two blocks to speed up the partial product generation and Wallace Tree reduction scheme speed up the partial product addition process by eliminating the carry chain of the addition. Radix-4 Booth encoding scheme Vedic multiplier with and without Wallace Tree partial product reduction scheme for signed and unsigned multiplication was designed and synthesized in Synopsys 130 nm technology. For unsigned multiplier, the Booth-Vedic multiplier is 37.29% faster and 26.13% smaller while the Booth-Vedic-Wallace multiplier is 39.79% faster and 28.81% smaller when compared with Vedic multiplier. The performance of both multipliers was dropped when used in signed multiplication due to signed extension during the partial product addition process. All the multiplier is functionally verified using modified testbench that is based on the concept of UVM testbench.

A Fast Multiplication Approach Using a Tree-Based Structure

This paper presents a technique for integer number multiplication using a tree-based structure. In the proposed method, both the generation of the partial products and the addition of partial products are completed in the tree structure. The proposed multiplication approach has been designed in two steps: Firstly, the partial products are generated in a tree-based structure using the fewest numbers of gates. Secondly, diagonal partial products additions have been done by the partial products residing in the diagonal partial product nodes to get a faster multiplication result, where two partial product nodes Pi , and Pk,l are diagonal only if |i - k| = |j - l|where i and k are the multiplicand bits; and j and l are the multiplier bits. The comparative study shows that the proposed multiplication algorithm outperforms the existing techniques; e.g., the proposed 4 × 4 multiplication algorithm improves 50% on the worst case running time complexity over the best known existing ones.
 GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 20-26

An Efficient VLSI Design of 32X32 bit Multiplier using Wallace Tree Algorithm in Vivado HLS and Xilinx ISE Software using VHDL

Multiplier is the most basic component present in any digital system. These multipliers are mainly used in Digital Signal and Image Processing applications. In applications like image detection latest sophisticated algorithms like CNN are used which contains MAC units in their design. The multiplier used in MAC unit requires huge memory, offers high latency and consumes more power. There are many algorithms such as Combinational, Sequential and Array Multiplication Algorithms which helps in designing Multiplier. The major drawback in all designs is circuit complexity. The problem of latency and power dissipation are also present. Considering all the drawbacks present in those algorithms this paper proposes the usage of Wallace Tree Algorithm which consumes less power and has low latency. Also, there are many ways to add the final stage of partial products generated such as Carry Look Ahead adder, Carry Select Adder etc. This paper uses both Carry Select Adder and Ripple Carry Adder for performing final addition of partial products. All previous partial products are added using Half adders and Full adders. The Multiplier is designed using VHDL in Xilinx ISE and Vivado Platform.

Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

Design of adder plays a major role in deciding overall performance of system as it is a major building block through generations of design in an innovative design of circuits. In VLSI system and signal processing field applications, various versions of adders are utilized. In applications of signal processing, in recent days, major role is contributed by Finite Impulse Response (FIR) filter. Various authors and papers described its design in a several ways. With the design of effective multiplier, signal denoising application was not explained by any of the existing works. For the generation of partial products, 8-bit multiplier based on a Vedic Mathematics –UrdhvaTiryagbhyam sutra- is proposed in this work. In Vedic multiplier, carry skip method is used for realizing addition of partial product. Four Vedic multipliers of 4 × 4 size are used for designing 8-bit multiplier. Carry skip and UrdhvaTiryagbhyam methods are used for this design. For addition of partial product, this multiplier is designed. Ripple carry adder's logic levels are modified for adding these Vedic multiplier's output. Powerful elimination of ECG noise can be done using this proposed fast FIR filter. In applications of healthcare and biomedical field, they are used. In Vedic design, Ripple Carry Adder (RCA) is used for carrying out partial product addition. Operation of FIR filter with Electro Cardiogram (ECG) signal is done by proposing architecture of FIR filter. It is termed as PPAVD-RCA-FIR and used in de-noising applications. From de-noised signal, Signal to Noise Ratio (SNR), Bit Error Rate (BER) and Mean Square Error (MSE) are computed, which are used for evaluating the performances. When compared with general Vedic multiplier, speed of the proposed design is increased about 13.65% as shown by results.

High throughput FIR filter architectures using retiming and modified CSLA based adders

A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.

Novel Architecture for Binary Multiplication

Multipliers is the basic unit for all signal processing applications and other applications. In all technology advancement it plays a vital role, the targets are low power consumption, increase in speed, reduction in area etc. The computations that are done by a modern computers that includes microcomputers and microprocessor is astronomical. Even with the high speed computer chips the process of the data coming from the devices all over the world requires efficient algorithms and to achieve the compatibility we need to use the chip area effectively. The most often encountered computation in data processing or signal processing is the operation of multiplication. This architecture is to present a novice solution to reduce the total area of the multiplier by modifying the partial products addition multiplier. Generally, to compute the data with high speeds modern hardware uses the Wallace tree or dadda multiplication techniques. By reducing the number of partial products addition the number of gates can be reduced used to obtain the final result. In this proposed method we reduced the real-estate of the chip by using more number of full adder in the earlier stages of the partial products addition which is not present in the conventional multipliers.

Efficient half-precision floating point multiplier targeting color space conversion

Color Space Conversion (CSC) in image processing applications, demands computationally simple floating point multipliers consuming less area and power. This necessitates the design and realization of the same meeting the aforesaid concerns. This paper makes one such contribution in the form of a New Bit Pair Recoding (NBPR) algorithm for realizing a Data Length Reduction (DLR)-based 16-bit Half-Precision Floating Point Multiplier (HPFPM). This algorithm with merged partial product addition achieves partial product height reduction from n to $\frac {n}{4}$ for an n × n multiplier by evading 2’s complement, negative encoding and sign extension. HPFPM is implemented on both Application Specific Integration Circuit (ASIC) with TSMC 180, 130 and 65 nm technologies and Xilinx-Virtex-5 and Virtex-7 Field Programmable Gate Array (FPGA) families. HPFPM synthesized on TSMC 65nm consumes 51% and 55.8% of area and power respectively, with 0.6835% error when compared with full width half-precision multiplier. Also, HPFPM for RGB-YUV-RGB and RGB-YCbCr-RGB conversion reduces the area, power consumption by 11%, 12% respectively, with 93.2% improved accuracy, when compared with truncated 32-bit single-precision floating point multipliers (SPFPMs). The converted image is evaluated using Peak-Signal-to-Noise-Ratio (PSNR) and Mean Square Error (MSE) in Matlab for quantifying HPFPM suitability for CSC in imaging.

Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors

Abstract In the modern electronic devices, compressor circuits are used to speed up the partial product addition (PPA) stage in the multipliers. This paper presents an architecture of multi-column 5,5:4 compressor whose new transistor level implementation has been carried out through the ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Such compressor has been simulated in Cadence-spectre, and the performance parameters like power consumption and delay has been calculated at the rising and falling edge transition of input pulses. Advantage of the UTBSOI-compressor is further clarified from its comparison with the CMOS based design (CMOS-compressor). Simulation results reveal that the PDP exhibited by the UTBSOI-compressor is reduced by 79.89% than that of CMOS counterparts. Furthermore, to showcase the advantage of such compressor, it has been applied in the multiplier for PPA which offers ≈11.5% improvement in terms of power-delay-product (PDP) in the Virtex 6 platform.

DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications

In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

Design of Finite Impulse Response Filter Architecture using Wallace Tree Multipliers

Finite impulse response (FIR) filter is one of the main key mechanisms in any communication systems. The output of the system is relates to the FIR filter, so need to design an efficient FIR filter, to get a perfect output. Filter design contains many blocks; one of the main blocks is multiplier. Many types of multipliers are available in the digital circuits, but need an efficient multiplier design to get better filters. Multiplier is one of the basic building blocks in the digital circuits. So the performance of the multiplier is important to get an efficient circuit design. Power consumption is one of the major drawbacks in the multiplier. Power consumed by the multiplier is higher in the digital circuits. Wallace tree multiplier was designed and implemented using verilogHDL. This multiplier reduces the stages of partial product addition. So this multiplier takes less number of gates to implement and also it overcomes the existing multiplier drawbacks. Finally the designed multipliers are applied into the FIR filter, and show the best filter.