Abstract
Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24- bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12- bit, and 24- bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24- bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.
Highlights
The squaring operation represents one of the most arithmetic operations in high-speed applications involved cryptography, animation, image compression, fast-Fourier transform (FTT), pattern recognition, adaptive filtering, and others [1,2,3]
It is found that Vedic-based squarer (VBS) circuits implemented utilizing IBK-carryselect adder (CSLA) with amended XOR gates give the finest outcomes in terms of delay and area in comparison with the other VBS circuits carried out with other adder designs, as depicted in Figures 9 and 10
It is observed that there is a direct relationship between the size in bits for the pipelined VBS and the system throughput in designing the 24- bit VBS and it is seen that as the VBS and the complexity of its related adder are reduce, the area of the VBS reduces, and the delay for computing the squaring result reduces, as well
Summary
The squaring operation represents one of the most arithmetic operations in high-speed applications involved cryptography, animation, image compression, fast-Fourier transform (FTT), pattern recognition, adaptive filtering, and others [1,2,3]. Utilizing dedicated squarer circuits can help improve the speed of various applications and enhance the general area of the structure [7]. Many designs and techniques were planned to implement binary squarer. The delay of the design had been reduced as the generation of partial products and the addition of the partial derivatives are computed simultaneously. The design area increased due to four Vedic multipliers (VMs) for squaring an n-bit binary operand. In [12, 13], authors have offered high-speed binary squaring circuits employing Urdhva Tiryagbhyam' Sutra (UTS) techniques. The courses' delay has been reduced, thereof the implementation utilized two squarer circuits, which led to an increase the device usage.
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