Abstract
In this paper, multiplication for single precision floating point numbers is analyzed using Vedic multiplier with different techniques. In Vedic multiplier, the full adder is designed using modified 2 × 1 and 4 × 1 multiplexers, 3:2 and 4:2 compressors, and various prefix adders, such as Brent-Kung, Sklansky and Knoules adders for partial products addition. Furthermore, the performance metrics in terms of area and delay comparison is done. From the results, it is concluded that compressor-based Vedic multiplier requires less hardware and prefix adder-based Vedic multiplier is better in terms of delay. The newly introduced changes in Vedic multiplier makes the Vedic multiplier better in performance for the floating point multiplication for single precision numbers using different methods. All modules are coded with Verilog Hardware Description Language and simulated with Xilinx ISE tool.
Published Version
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