Implementation and Analysis of Single Precision Floating Point Multiplication Using Vedic and Canonic Signed Digit Algorithm

Abstract

Multipliers are the most vital blocks in many digital applications, i.e. digital filters, Digital Signal Processors (DSPs). Further, multipliers are considered as crucial elements in Floating Point(FP) arithmetic operations which are widely used in the real time signal processing applications. The design of FP multiplier is relatively complex than integer multipliers. In floating point multiplication so far, many multiplier designs like array, Wallace and booth are embedded to improve the performance of the design. From the literature, it is inferred that no multiplier design provides satisfied performance with respect to all important performance metrics such as area, delay and power. Hence, in this paper, the design and analysis of single precision floating point multiplication with Vedic multiplier is presented by considering modified 2×1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing multiplier techniques. To achieve further improvement in the performance of single precision floating point multiplication with Vedic multiplier, Canonic Signed Digit CSD technique is incorporated in that floating-point multiplication to improve the hardware efficiency by using minimum number of adders (or subtractor) blocks. Moreover, this paper examines the optimized design methods of CSD multipliers by using different techniques which are used in the above-mentioned multiplier using Vedic. Further, the performance analysis of single precision floating point multiplier using Vedic and CSD is analyzed in terms of area and delay and also compared with that of different existing techniques. From the simulation results, it is observed that single precision floating point multiplication with CSD multiplier gives better performance than the floating-point multiplier using Vedic with and without modified techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.