Improvised hierarchy of floating point multiplication using 5:3 compressor

Abstract

ABSTRACT The main objective is to develop floating-point multiplication (FPM) using 5:3 compressor based Vedic multiplier (VM), Karatsuba algorithm (KA) and canonical signed digit (CSD) algorithm to overcome the drawbacks presented in conventional compressor based FPM. In this scenario, an attempt is made to enhance the performance of FPM using three efficient algorithms. Finally, the performance analysis in terms of area, delay and power dissipation of using VM, KA and CSD with 5:3 compressor are examined and compared. The designs f00which are involved in mantissa multiplication are coded in Verilog HDL and implemented using Xilinx Vivado. It is clearly convinced from the 5:3 compressor based CSD that it provides better performance than other two algorithms by achieving acceptable area and delay. Single precision floating point multiplication (SPFPM) using Vedic with 5:3 compressor requires 29% Look Up Table (LUT) area and 30% slice area improvement in comparing with KA. In case of delay, KA gives 35% improvement compared to vedic based SPFPM. For CSD algorithm based SPFPM requires 46% improvement in LUTs area and 49% improvement in Slice area compared to KA based SPFPM.