Adder Module Research Articles

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 NMOS and 8 PMOS. A PTL and GDI full adder module has been used which consume less area at 120 nm as compared with the previous full adder designs. The proposed Hybrid 1bit comparator design is based on this area efficient 9T full adder module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used full adder module. Full adder modules outputs have been used for the generation of three different output of 1-bit comparator designs. The proposed 1-bit comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit comparator design. Power and current variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 329.3μm on 120nm technology. At 1.4V input supply voltage the proposed 1-bit hybrid comparator consume 0.367mW power at BSIM-4 and 0.411mW power at LEVEL-3 and 2.313mA current at BSIM-4 and 3.047mA current at LEVEL-3 model

New High-Speed Multioutput Carry Look-Ahead Adders

In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

High Performance FPGA Implementation of Floating Point Addition

Addition is the most frequent floating point operation in modern microprocessors. The design of floating point addition is relatively complex than other flotation point arithmetic operations. Due to its complex shift-add-shift-round data flow, floating point addition can have a long latency. This paper has shown an efficient implementation of addition module on a reconfigurable platform cyclone IV EP4CE15, which is both area as well as performance optimal. The proposed design has optimized the individual complex components of adder module (like dynamic shifter, leading one detector (LOD), priority encoder), to achieve the better overall implementation. Comparison with the best reported.

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new full adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit.Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new full adders in a real environment, we incorporated two 16-bit ripple carry adders (RCA). The studied circuits are optimized for energy efficiency at 0.13µm and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard full adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).

Systematic Analysis on Power Consumption in Conventional Cmos, Multiplexer Based and Hybrid Adder

There has been a rapid increase in the popularity of portable and wireless electronic devices, like laptop computers, portable video players cellular phones, which rely on embedded digital signal processors. Since the desire is to design digital systems at best performance without power sacrifices, the need for high performance and low power multipliers is inevitable. Since multiplication is one of the most critical operations in many computational systems, Multipliers are in fact complex adder arrays. In this paper we performed a comparative analysis on power consumption in three different adders, each offering different advantages and having tradeoffs in terms of circuit complexity and power consumption. The 28 Transistor full adder is the pioneer CMOS traditional adder circuit. Which is the one which consume more power when compare to other two adder, the number of transistors required for conventional CMOS adder is 28. Recently, it has been proved that the multiplexer-based multiplier outperforms the modified Booth multiplier both in speed and power dissipation by 13% to 26%, due to small internal capacitance. After analyzing the performance characteristics of conventional multiplier types, it is observed that the one designed using multiplexer-based multiplication algorithm is more advantageous, especially when the size of the multiplied numbers is small. The number of transistors required for multiplexer based adder is 16. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. The hybrid adder models which consume low power among all three adder and the number of transistors required is 12. As an added advantage there will be no path from one voltage level (VDD) to the other (GND).The elimination of the direct path to the ground removes the short circuit power component for the adder module. This reduces the total energy consumed in the circuit and making it an energy efficient design. The SERF adder is not only energy efficient but also area efficient due to its low transistor count.

HEADPHONE SURROUND USING ARTIFICIAL REVERBERATION

A surround experience for headphones can be created using various techniques and tools. The described techniques and tools can be applied separately or in combination. For example, a surround experience can be created by splitting input audio channel signals into high-pass and low-pass signals. The low-pass signals can undergo cross-mixing and artificial reverberation. The artificial reverberation can apply different delay profiles to the low-pass audio signals. The high-pass and low-pass audio signals can be combined to generate output audio channel signals. A surround experience can be crated using a system comprising an input module, a crossover module, a channel cross-mixing module, a reverberation module, and an adder module.

An Arithmetic System over Finite Fields

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of <TEX>${\alpha}^k$</TEX> terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing <TEX>${\alpha}^k$</TEX> generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

感应电压叠加器模块对方波脉冲的响应

感应电压叠加器模块对方波脉冲的响应

Algorithm for designing efficient VLSI concurrent add-multiply and add-multiply-add cells for DSP applications

A new algorithm is presented to (i) multiply two operands represented in hybrid notation, namely, one as a single vector and the other as two carry-save vectors of logic ‘1’s and ‘0’s, and (ii) to minimise and subsequently add the resulting sign extension bits concurrently with (i). The use of the proposed algorithm results in the complete elimination of the need for the separate adder modules normally used in conventional schemes for implementing add-multiply, add-multiply-add, add-multiply-add-multiply, dual-multiply operations frequently encountered in many DSP applications. Design examples are presented for illustrative purposes.

Optical Module for Modified Signed-Digit Computing Based on Bit Plane Encoding and Pattern Operations

We propose here a new optical modified signed-digit (MSD) adder module based on bit plane pattern encoding of MSD digits and pattern operations. The pattern operations required in the algorithm are duplication, combination and shifting. They are simply performed by using optical components such as beam splitters, mirrors and parallel plates, instead of optical logic arrays. An optical MSD adder module comprised of six properly interacting blocks with all optical components packaged on a common substrate is presented in detail. We analyze the system errors caused by manufacture and alignment of optical components, the information throughput, the intensity nonuniformity and the system volume of the adder module.

Hierarchical mapping of spot defects to catastrophic faults-design and applications

This paper describes the defect to fault mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164 K transistors. Test quality analysis results are given for an adder module. >

Studies of light ion beam for inertial confinement fusion by induction adder

Light ion beams for the energy drive for inertial confinement fusion (ICF) research have been studied on a super high voltage generation system (SHVS) using an inductive voltage adder system. A simple analysis implied the capability of the output voltage of several tens of MV. This system has a feasibility of acceleration of ions heavier than proton. The two-stage charge stripping ion diode is considered a SHVS diode. This diode reduces the size of the induction adder module and extends the possible power range in operation. We have constructed a prototype SHVS, which consists of eight stages of induction cavities (4MV, 40kA, 100ns) powered by a Reiden IV pulse power machine. The first ion diode experiments on the induction adder were performed with the beam extraction type ion diode (Br applied magnetic field). The injection plasma ion source was used to control the diode impedance and then the diode voltage. The time delay of ion current turn-on was reduced from 15–20 ns to less than 5 ns by this ion source.

High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b*16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2- mu m CMOS double-metal technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On a Bit-Serial Input and Bit-Serial Output Multiplier

A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.

Logic Networks of Carry–Save Adders

logic networks of carry–save adders such as high-speed multipliers, multioperand adders, and double-rail input parallel adders are designed based on the parallel adders with a minimum number of NOR gates discussed in [1]. After a discussion of the derivation of carry–save adder modules (CSAM's) by the integer programming logic design method, general design procedures are illustrated with example networks. Compared to conventional networks of carry–save adders, the derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation. In particular, the parallel adder of NOR gates in double-rail input logic obtained has six gates and 15½ connections per stage, whereas the previously known best design under the same condition requires six gates and 17 connections per stage with the same carry propagation delay.