Abstract
Addition is the most frequent floating point operation in modern microprocessors. The design of floating point addition is relatively complex than other flotation point arithmetic operations. Due to its complex shift-add-shift-round data flow, floating point addition can have a long latency. This paper has shown an efficient implementation of addition module on a reconfigurable platform cyclone IV EP4CE15, which is both area as well as performance optimal. The proposed design has optimized the individual complex components of adder module (like dynamic shifter, leading one detector (LOD), priority encoder), to achieve the better overall implementation. Comparison with the best reported.
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