Systematic Analysis on Power Consumption in Conventional Cmos, Multiplexer Based and Hybrid Adder

Abstract

There has been a rapid increase in the popularity of portable and wireless electronic devices, like laptop computers, portable video players cellular phones, which rely on embedded digital signal processors. Since the desire is to design digital systems at best performance without power sacrifices, the need for high performance and low power multipliers is inevitable. Since multiplication is one of the most critical operations in many computational systems, Multipliers are in fact complex adder arrays. In this paper we performed a comparative analysis on power consumption in three different adders, each offering different advantages and having tradeoffs in terms of circuit complexity and power consumption. The 28 Transistor full adder is the pioneer CMOS traditional adder circuit. Which is the one which consume more power when compare to other two adder, the number of transistors required for conventional CMOS adder is 28. Recently, it has been proved that the multiplexer-based multiplier outperforms the modified Booth multiplier both in speed and power dissipation by 13% to 26%, due to small internal capacitance. After analyzing the performance characteristics of conventional multiplier types, it is observed that the one designed using multiplexer-based multiplication algorithm is more advantageous, especially when the size of the multiplied numbers is small. The number of transistors required for multiplexer based adder is 16. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. The hybrid adder models which consume low power among all three adder and the number of transistors required is 12. As an added advantage there will be no path from one voltage level (VDD) to the other (GND).The elimination of the direct path to the ground removes the short circuit power component for the adder module. This reduces the total energy consumed in the circuit and making it an energy efficient design. The SERF adder is not only energy efficient but also area efficient due to its low transistor count.