Adder Design Research Articles

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

PurposeIn nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.Design/methodology/approachThis paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.FindingsA new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.Originality/valueThis paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

Comparison between CMOS full adder and PTL full adder

In electronic industry the level of integration is an important aspect as makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, area occupied and delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Designing of full adder using conventional CMOS design and PTL has been shown in this paper. A comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Mentor Graphics Tool is used in design and simulation of the full adder. The PTL full adder has a smaller number of transistors and lower power dissipation compared to CMOS full adder. With all the comparison made it will be concluded that the PTL full adder performance is better than the CMOS full adder.

Design of Compact and Smart Full Adders for High-Speed Nanometer Technology IC’s

It is intensely acknowledged that the key handing out unit of any device competent of carrying out computations is the CPU (Central Processing Unit) and one of the most elementary and central parts of CPU is an ALU (Arithmetic and Logical Unit). The ALU is primarily responsible for carrying out the logical operation, arithmetic operations etc. The proposed full adder has low power consumption and better area efficiency. Post layout simulations using the Mentor graphics tool have been evaluated. The circuits proposed are extremely optimize in terms of transitor switching power and latency, due to small load capacitance and low dissipation of short circuit electricity. Each of the suggested and simulated circuits has its own benefits of speed, power Dissipation, Power Delay Product (PDP), and driving capability. The circuits proposed are studied in terms of voltage input and threshold voltage variations, output load variations, signal to ratio with respect to transistor scaling.

An Enhanced Self-checking Carry Select Adder Utilizing the Concept of Self-checking Full Adder

In this paper, an enhanced self-checking carry select adder (CSeA) architecture is introduced. However, we first show that the carry select adder design presented literature does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.

A Novel Efficient CNFET-Based Inexact Full Adder Design for Image Processing Applications

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

A systematic design of novel energy efficient 64-bit parallel-prefix adder

ABSTRACT Advancement in CMOS technology demands to revamp the design of basic functional units in digital systems. The binary addition is the basic operation in digital units like microprocessors, digital signal processors and data processing units in ASICs. Scaling down the technology no longer supports power density and energy-efficient digital architectures. The energy-efficient adder design demands the exploration of recurrence structures, existing algorithms, circuit design techniques, system constraints, energy and delay trade-offs. This paper presents the systematic design approach towards the design of an energy-efficient 64-bit parallel-prefix adder. A novel two-bit sum block reduces the power dissipation and the proposed recurrence algorithm further optimises the overall energy consumption. The 64-bit adder is implemented in static CMOS design and simulated in 45, 32, 22 and 16 nm technology nodes to validate the energy efficiency. In 45 nm technology, the proposed 64-bit parallel-prefix adder consumes 64.61% and 15.3% less energy compared to Brent–Kung and Ling adder respectively whereas in 16 nm technology, the proposed adder consumes 57.54% lesser energy than Brent–Kung adder and 14.28% lesser energy compared to the Ling adder.

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.

Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology

Quantum dot cellular automaton (QCA) is a novel emerging nanometer-scale-based circuit design using nanocomputing technology, which overcomes the limitations of complementary MOS technology in the precondition of the circuit design area, power, and latency/delay. This paper presents an efficient design of crossover single-layer (coplanar) and multilayer novel hybrid full adder–subtractor circuits by implementing majority gate minimization functional J-map technique. The proposed circuits have been found more efficient in terms of minimum number of QCA cells, low latency, required area in µm2, and reduced quantum cost as compared to existing QCA adder–subtractor designs and also avoid the thermodynamics problems occurring due to long QCA wires with the applied synchronization clocking method. In this paper, we have introduced 14 nm × 14 nm and 16 nm × 16 nm cell size QCA circuits and compared with an existing and proposed novel 18 nm × 18 nm single-layer and multilayer designs. Both designs are implemented by the QCADesigner-E tool with bistable vector and coherent vector energy setup in the Euler method and the Runge–Kutta method.

A New Design of a Carry-Save Adder Based on Quantum-Dot Cellular Automata

A New Design of a Carry-Save Adder Based on Quantum-Dot Cellular Automata

A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. Particularly, the proposed carry prediction technique can reduce a prediction error rate by up to 75% compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). Our experimental results show that the proposed adder improves the normalized mean ED (NMED) and mean relative ED (MRED) by up to 91.4% and 98.9%, respectively, compared to the other approximate adders. Importantly, an excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Specifically, the proposed adder achieves up to 95.7%, 91.1%, and 93.2% reductions of the power-NMED, energy-NMED, and area-delay product (ADP)-NMED products, respectively, compared to the other adders. Our adder enhances the power-, energy-, and ADP-MRED products by up to 99.4% compared to the others. In particular, the figure of merit (FoM) considering both hardware and accuracy of the proposed adder is up to 93.05% smaller than that of the other approximate adders considered herein. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.

An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> and less than 1/10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> the off-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (LVT) and High V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.

Design of All-Optical Half Adder and Half Subtractor based on SOA-MI

An all-optical half adder and half subtractor is proposed using Semiconductor Optical Amplifier assisted Michelson Interferometer (SOA-MI) configuration along with two similar Fiber Bragg Grating (FBG) at the end of the interferometric arms to satisfy the truth table of half adder and half subtractor. SOA acts as an amplifier without the need for conversion to electrical signals. The proposed model is designed using all-optical NOR gates with cross-gain modulation (XGM) of SOA at bit rate of 10Gbps. Analysis of performance factors which includes Bit Error Rate (BER), OSNR and Q-factor have been discussed.

Characteristics of Parallel Carry-Free Three-Step MSD Additions

Since the modified signed digital (MSD) redundant representation was proposed in the 1950s, lots of achievements have been made in MSD arithmetic. By inspecting the processes of the parallel carry-free three-step MSD addition, the transformations for such additions are studied in detail in this paper. The characteristics for parallel carry-free three-step MSD addition are proposed and the correctness is proved. Then seven groups of transformations that have characteristics of three-step MSD addition are presented. These groups of transformations are dual or self-dual, and some of them have simpler forms than the typical transformations consisting of $T, W, T', W', T_{2}$ . The general design mode of parallel carry-free three-step MSD additions and its applications in ternary optical computer (TOC) are further proposed. At the same time, single adder (multi-adder) reconstruction mode, processor bits allocation strategy, and light path diagrams are given. The optical experiments of MSD additions for three groups of MSD addition transformations show that the results of these transformations are correct. This work provides the theoretical basis for the design of the ternary optical computer adder.

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner, the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area. This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing. We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model. Four case studies were used to assure the validity of the proposed adder. These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

Efficient stable-width adder-sapling strategy using Brent Kung adder

Abstract Addition is energetic arithmetic operation and is the base of other arithmetic operations like multiplication, subtraction and division. Adder could be advanced circuit that does expansion of twofold numbers. Gadgets with less control utilization and great execution are continuously favoured. Parallel Prefix adders are broadly utilized in computerized plan. This can be fundamentally since of the flexibility preparation in the adders. Brent Kung Adder employments less circuitry to get the result. The main concept of the paper, so as to diminish area and delay as well as power compared to existing work. In this paper we present Brent Kung Adder Plantlet structure and compared with modified full adder and ripple carry adder. Proposed structure (BKA) is an advanced binary adder design. Arrangement using straightforward otherwise post-decrease procedure. In straightforward or else boundary marker diminishments, retiring inferior ask bit from each adder give up of full-broadness adder sapling is post-abbreviated. At that point the condition of straight-decrease, lower mastermind pieces of convincing stage adder produce stay abbreviated. Both these strategies don't give a capable arrangement. In this brief, another arrangement is shown to obtain fixed-expansiveness BK-AS resolution using abbreviated data. The most raised precision in the current consistent broadness AS. The complete strategy synthesized and simulated by using Xilinx ISE 14.7 by using Verilog HDL.

Carry Select Adder Design with Testability using Reversible Gates

Carry Select Adder Design with Testability using Reversible Gates

BCD Adder Designs Based on Three-Input XOR and Majority Gates

Lots of emerging techniques can natively realize majority-of-three (MAJ) gates. Although enhanced gates such as exclusive-OR (XOR) gates can be implemented by several MAJ gates, there exists much efficient XOR design which directly derived by the physical attributes of emerging techniques. In this brief, we proposed multi-digit binary coded decimal (BCD) adder designs represented based on three-input exclusive-OR (XOR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) and MAJ gates. BCD adder is widely used in financial, commercial, and industrial computing. We implemented the designs using quantum-dot cellular automata (QCA) technology. The proposed logic representations are validated using different types of binary adders as well as QCA design strategies. The introduction of XOR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gates is conducive to achieve compact logic representations, which positively affect both the area and delay of QCA layouts. Compared with the existing best designs, the proposed 1-digit BCD adder has 50% less area and 10% less delay, and the 8-digit BCD adder has a 3.42× improvement of area-delay product.