A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

High-performance, energy-efficient, and memory-efficient FIR filter architecture utilizing 8x8 approximate multipliers for wireless sensor network in the Internet of Things

This paper presents a new approximate adder design to improve the computation accuracy of the conventional error tolerant adder by leveraging a carry prediction technique with a sum generator. The proposed carry speculation scheme exploits inputs from a single bit position and effectively increase the bit width of the accurate addition. Implemented in a 65-nm CMOS technology, the proposed approximate adder is up to two times faster than, and twice as power efficient as, the traditional adders. Compared to the other approximate adders considered in this paper, the proposed adder achieves up to 3.7%, 15.5%, 79.9% and 79.9% reductions in the error rate (ER), mean relative error distance (MRED), mean error distance (MED) and normalized MED (NMED) respectively, at an extra cost of merely 4% to 6% in area, delay, and power. In addition, the proposed adder offers a good tradeoff between power/energy and accuracy and improves on power/energy-NMED products by up to 46%, outperforming other approximate adders.

This paper proposes an approximate adder that employs a novel carry speculation scheme to enhance the computation precision of the existing error tolerant adder (ETA) designs with extremely little hardware overhead. The proposed carry prediction technique leverages two input bits to increase the prediction accuracy while the conventional ones do only one bit. This leads to a reduction of the carry prediction error rate from 25% to 18.75%. Compared to the existing ETA design, the proposed adder reduces normalized mean error distance (NMED) and mean relative error distance (MRED) by up to 10% and 28%, respectively, at the cost of only a two-input OR gate. Moreover, the proposed design outperforms the conventional ETAs when jointly evaluating hardware cost and computation accuracy. Specifically, the new design allows 11% and 17% reductions of area-power-NMED and power-NMED products, respectively, compared to the traditional ETA.

This paper proposes a novel approximate adder that exploits only a single input pair for approximation using a few logic gates. The mean error distance (MED) and mean relative error distance (MRED) of our adder are significantly better than those of other approximate adders considered herein. With a 65-nm CMOS technology, the proposed design also achieves 21% and 12% improvements in area and power, respectively, in comparison to other approximate designs. Moreover, our adder shows higher image quality in digital image processing than other approximate adders while consuming similar hardware costs.

Approximate computing has recently emerged as a promising paradigm to achieve considerable energy savings at the expense of degraded computing accuracy. In this paper, an approximate adder is proposed to reduce the power consumption while providing minimal computation errors for loop accumulation, which is a crucial operation in various signal processing algorithms. The proposed adder is based on smart modification of Karnaugh map to generate compensation effect with loop accumulation. With the proposed approximate adder, the power consumption is reduced by up to 42.8% and 24.9% compared to fully-accurate adder and the previously published approximate adders, respectively, in an industrial 65-nm CMOS technology. Furthermore, the computation accuracy is enhanced by up to 31x with the proposed approximate adder compared with the previously published approximate adders. Using the product of normalized mean error distance (NMED) and power consumption as the Figure-of-Merit (FoM), the proposed approximate adder improves the FoM by up to 37.7x compared to the previously published approximate adders.

Adders play a critical role as primary modules in circuit design, supporting error-tolerant applications such as machine learning, digital image processing, and signal processing. Therefore, the development of adders with low power consumption and energy efficiency is of utmost importance. Approximate adders outperform exact adders in VLSI chips. Among approximate adders, the hybridization of Single Exact and Single Approximation (SESA) and Single Exact and Dual Approximation (SEDA) techniques has emerged as a promising solution. These hybrid adders offer superior power and energy savings relative to other accurate and approximate adder designs. In this scheme, we propose the integration of hybrid radix-4 adders with approximation adders to achieve enhanced performance and pave the way for future hybrid approximate adder circuits. Extensive simulations validated the efficacy of the proposed approach. Furthermore, practical applications demonstrated the versatility and potential of hybrid adders in real-world scenarios. The proposed methodology ensures cost-effectiveness and facilitates seamless future updates and extensions. Overall, this research contributes to the advancement of efficient and low-power adder designs, addressing the evolving requirements of modern digital systems.

Approximate adder design has drawn wide attention as it can achieve good trade-offs between computation accuracy and cost. We observe that all existing approximate adders may produce completely incorrect result with up to 100% relative error. The big errors happen when higher bits have inconsistent views on certain lower carry-ins due to long carry chain. In this paper, we build a theoretical model to efficiently estimate the error characteristics of approximate adders. Furthermore, we present a novel approximate adder design with provable relative error bound by enforcing global carry consistency in long carry chains. Experimental results validate our theoretical model and demonstrate that our design outperforms start-of-the-art approximate adders.

Approximate adder design has drawn wide attention as it can achieve good trade-offs between computation accuracy and cost. We observe that all existing approximate adders may produce completely incorrect result with up to 100% relative error. The big errors happen when higher bits have inconsistent views on certain lower carry-ins due to long carry chain. In this paper, we build a theoretical model to efficiently estimate the error characteristics of approximate adders. Furthermore, we present a novel approximate adder design with provable relative error bound by enforcing global carry consistency in long carry chains. Experimental results validate our theoretical model and demonstrate that our design outperforms start-of-the-art approximate adders.

Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.

The demand for high performance computing is on the rise with the dominance of applications that process big data. Most of these applications are dominated by arithmetic operations, primarily multiplication and addition. Many of these algorithms, e.g., in the machine learning domain, can tolerate some amount of arithmetic error, especially in the low-order bits. Hardware designers can leverage this observation to simplify the hardware design. Although prior work has demonstrated the benefits of approximate arithmetic in the context of one-off hardware designs, what is presently lacking is a systematic methodology to generate highly-optimized arithmetic components that meet a user-specified level of error tolerance. This paper introduces one such tool, which generates single-cycle approximate adders along with speculative adders which perform multicycle error correction. The underlying intellectual contribution is a family of approXimate 1-bit Full Adders (XFAs), which vary in terms of accuracy, delay, area, and power consumption. Our tool, CAL, constructs larger adders using XFAs as building blocks, effectively allowing the user to sacrifice accuracy in order to improve the three aforementioned metrics. The experimental analysis demonstrates improvements in both accuracy and efficiency compared to state-of-the-art approximate adder designs published by others, and validates the capabilities of our speculative implementations.

Approximate computing is an emerging paradigm to improve the power and performance efficiency of error-resilient applications. As adders are one of the key components in almost all processing systems, a significant amount of research has been carried out toward designing approximate adders that can offer better efficiency than conventional designs; however, at the cost of some accuracy loss. In this article, we highlight a new class of energy-efficient approximate adders, namely, Heterogeneous Block-based Approximate Adders (HBAAs), and propose a generic configurable adder model that can be configured to represent a particular HBAA configuration. An HBAA, in general, is composed of heterogeneous sub-adder blocks of equal length, where each sub-adder can be an approximate sub-adder and have a different configuration. The sub-adders are mainly approximated through inexact logic and carry truncation. Compared to the existing design space, HBAAs provide additional design points that fall on the Pareto-front and offer a better quality-efficiency tradeoff in certain scenarios. Furthermore, to enable efficient design space exploration based on user-defined constraints, we propose an analytical model to efficiently evaluate the Probability Mass Function (PMF) of approximation error and other error metrics, such as Mean Error Distance (MED), Normalized Mean Error Distance (NMED), and Error Rate (ER) of HBAAs. The results show that HBAA configurations can provide around 15% reduction in area and up to 17% reduction in energy compared to state-of-the-art approximate adders.

Approximate Computing has emerged as a propitious solution for faster, energy-efficient and less complex designs for circuits. Approximate arithmetic circuits are a type of circuit that achieves power and area efficiency by intentionally introducing imperfections into circuit’s output behavior. In arithmetic circuits adder plays a prominent role. It has become essential to understand the approximation techniques and methods to enhance performance and efficiency. This paper aims to provide a comprehensive review on approximate adders and comparatively assessed in terms of error and performance based on speed, area and power. Arithmetic circuits are implemented and synthesized using HDLs and design compiler and error characterization is done by using MATLAB. In this paper power, speed and area are compared with respect to error distance, normalized mean error distance and mean relative error distance. The comparative result conveys that equal segmentation adder has low accuracy but it is a hardware efficient design. After evaluation analysis conveys that equally accurate adders are error-tolerant adder type II, Speculative carry select adder and the accuracy configurable approximate adder. In this most power consuming adder is almost the correct adder. Among all adders, the slowest and extremely efficient adder is the lower part OR adder.KeywordsApproximate computingArithmetic circuitsAdderError characteristicsEvaluation

Energy-efficient and high-performance general- purpose compute engines, as well as application specific integrated circuits, are highly demanded to facilitate the development of artificial intelligence and big data processing applications. However, with the end of Dennard’s scaling and Moore’s law it is becoming difficult to handle massive amounts of data and complex computations required in these applications. Approximate computing (AC) has emerged as an attractive paradigm in the digital design to address this unprecedented challenge. AC is driven by the observation that many state-of-the-art applications, such as classification, machine learning, data mining, robotics and communication, exhibit error-tolerant characteristics; therefore, a small amount of error (trades off the requirement of exact computation) can be introduced to achieve area, power, and speed benefits. AC techniques can be applied at both the software and hardware layers. At the hardware layer, arithmetic units (multipliers, adders, and dividers) are considered as hardware computational modules. Therefore, the approximation at hardware layer has been focused around the design of approximate arithmetic units. This paper presents approximate multipliers based on novel 4:2 compressors for error-tolerant applications. The proposed 4:2 compressors exhibit zero-mean error behavior while having a comparable hardware utilization with the existing state-of the-art designs. The hardware-efficient as well as the error-efficient designs of variable accuracy-power has been investigated to explore the maximum trade-off. All the designs are synthesized using Cadence Genus synthesis tool (TSMC 65 nm technology) and power is reported using Cadence Joules RTL power solution. A comprehensive error analysis is performed using well-known error metrics such as error distance (ED), mean average distance (MED), mean relative error distance (MRED) and normalized mean error distance (NMED). Moreover, all the designs are also compared with respect to power-delay product (PDP) and MRED to apprehend which designs are lying on the error-energy Pareto- optimal curve. A case study is also presented to demonstrate the applicability of the proposed designs in practical image processing application.

Matrix multiplication (MM) is a basic operation for many Digital Signal Processing applications. A Systolic Array (SA) is often considered as one of the most favorable architecture to achieve high performance for matrix multiplication. In this paper, the design exploration for an approximate SA is pursued; three design schemes are proposed by introducing approximation in multiple sub-modules. An approximation factor $\alpha$ is introduced; it is related to the inexact columns in the SA to explore the accuracy-efficiency trade-off present in the proposed designs. In the evaluation, an 8-bit input operand matrix multiplication is considered; the Synopsys Design Compiler at 45nm technology node is used to establish hardware-related metrics. The Error Rate (ER), Normalized Mean Error Distance (NMED) and Mean Relative Error Distance (MRED) are used as figures of merit for error analysis. Results show that the proposed architecture for 8-bit matrix multiplication with an approximation factor $\alpha=7$ has the lower power consumption compared to existing inexact designs found in the technical literature with comparable NMED. In addition, a power delay product vs NMED analysis shows the proposed designs have a lower PDP so applicable to low power applications. The practicality of the proposed architecture is established by computing the Discrete Cosine Transform.