Analog-to-digital Research Articles

Inverter-based noise-shaping SAR ADC for low-power applications

Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

A 3.58 nJ/Node Dual Cross Correlation Analog-Front-End Circuit With ADC for Mutual Capacitive Panel

This article presents a dual cross correlation analog-front-end (DCC-AFE) circuit for a mutual capacitive panel. The DCC-AFE circuit solves the problem of reduced recognition ability owing to the phase difference variation between the transmitted and received signals for a large load panel. A sparse collection algorithm is adopted to reduce the number of analog-to-digital converter (ADC) collections and microcontroller unit (MCU) operations in the proposed touch system. Only a 12-bit successive-approximation-register voltage-controlled-oscillator (SAR-VCO) ADC could meet the requirement. Based on this algorithm, both the power consumption and die area of the proposed analog-front-end (AFE) are significantly reduced. Moreover, we propose a calibration algorithm to improve the accuracy of the ADC. The proposed state-of-art touch integrated circuit (IC) was fabricated via a 110 nm CMOS process. The proposed AFE achieves 46.1 and 50.2 dB signal-to-noise ratio (SNR) with 384 and 128 Hz frame rates, respectively. The active area of the 64-channel AFE with ADC on the chip is 0.988 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , which only occupies a small area. The touch IC has an energy consumption of 3.58 nJ/node.

Linearisation of Digital-to-Analog Converters by Model Predictive Control

Digital-to-analog converters (DACs) are used to reconstruct digital quantised signals in the analog domain. Practical DACs exhibit several non-ideal effects; principally integral non-linearity (INL). INL is caused by element mismatch, meaning actual output levels deviate from the ideal, causing distortion. To reduce this error, a method employing moving horizon optimal control is proposed, where INL has been integrated into the model. The model is built by precisely measuring the INL of the physical device and organising the data into a lookup table. Previous attempts at using moving horizon optimal quantiser (MHOQ) have assumed ideal quantisation and are therefore unable to reduce the impact of INL. Several other methods exist that can linearise and mitigate the impact of INL but have significant drawbacks, such as a lack of guaranteed stability, complexity, and the need to use specialised and custom circuit topologies that cannot be replicated with of-the-shelf equipment. The effectiveness of the proposed method is demonstrated via simulations and experiments on an of-the-shelf DAC.

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Design And Development of an Application to Preserve Various Eatables Using IoT

The presented research relates to an IoT based device for sensing quality of food items using sensors, and more particularly relates to a device which shows its results through a mobile application, and further the user can check the quality of food item on his/her mobile device and proposes the work done in shooting up the efficiency of a device that detects the presence of different parameters in a food item on which it is judged to be fresh or tainted, at an early stage with the help of sensors, basically alerting us that if the food item is fine to consume or not. Due to the increasing number of food-borne diseases globally, the detection of food consumption has become an essential aspect of modern life. The system includes, but not limited to, a plurality of sensors for sensing varied parameters of a food item; a microcontroller unit for processing the signal received from the sensors; a mobile interface to show the results for freshness and quality about the food items. Different sensors detect the freshness of different food items based on various parameters like moisture, ethanol and alcohol content and humidity in the environment. Eat Fresh device mainly consist of a node microcontroller unit (MCU) and different types of sensors like ethanol sensor, humidity sensor, moisture sensor. The analogue results are passed to the pins of the Node microcontroller unit (MCU) which already have an inbuilt ADC (analogue to digital converter) that converts the analogue value to digital value. This device ‘Eat-Fresh’ is capable enough to help us check the safety of the food. Hence, preventing deaths due to food poisoning and helping us to put a stop on the wastage of food.

New digital low-level RF controls based on the Red Pitaya STEMlab for the TLS Linac system

The Linac system at Taiwan Light Source (TLS) has been in operation for almost a quarter of a century and requires upgrades to improve its reliability. To achieve this, some components of the control system have been replaced with new digital low-level RF control units that use emerging technologies. A new unit is based on the open-source hardware platform which is named “Red Pitaya STEMlab” and offers a compact size and low power consumption. The unit features DAC (Digital-to-Analog Converter) blocks for downloading arbitrary waveforms with external trigger play and ADC (Analog-to-Digital Converter) blocks for waveform acquisition, enabling the development of real-time diagnostic toolkits. The new low-level RF control interface has been fully integrated into the existing EPICS software framework for system integration. The new digital low-level RF control system supports I/Q (in-phase/quadra-ture-phase) data with online amplitude and phase set-tings, and a waveform digitizer for inspecting low-level RF signals from the klystron modulator. Specific graphical applications have been designed and integrated into the existing operation interfaces. The system has been successfully achieved during routine operations. This paper describes the details of these efforts.

3D Position Tracking Using On-Chip Magnetic Sensing in Image-Guided Navigation Bronchoscopy.

This paper presents a compact and low-cost on-chip sensor and readout circuit. The sensor achieves high-resolution 5-degrees-of-freedom (DoF) tracking (x, y, z, yaw, and pitch). With the help of an external wire wound sensor, it can also achieve high-resolution 6-degrees-of-freedom (DoF) tracking (x, y, z, yaw, pitch, and roll angles). The sensor uses low-frequency magnetic fields to detect the position and orientation of instruments, providing a viable alternative to using X-rays in image-guided surgery. To measure the local magnetic field, a highly miniaturised on-chip magnetic sensor capable of sensing the magnetic field has been developed incorporating an on-chip magnetic sensor coil, analog-front end, continuous-time ∆Σ analog-to-digital converter (ADC), LVDS transmitter, bandgap reference, and voltage regulator. The microchip is fabricated using 65 nm CMOS technology and occupies an area of 1.06 mm 2, the smallest reported among similar designs to the best of our knowledge. The 5-DoF system accurately navigates with a precision of 1.1 mm within the volume-of-interest (VOI) of 15 ×15 ×15 cm 3. The 6-DoF system achieves a navigation accuracy of 0.8 mm and an angular error of 1.1 degrees in the same VOI. These results were obtained at a 20 Hz update rate in benchtop characterisation. The prototype sensor demonstrates accurate position tracking in real-life pre-clinical in-vivo settings within the porcine lung of a live swine, achieving a reported worst-case registration accuracy of 5.8 mm.

A 10-Channel, 120 nW/Channel Reconfigurable Capacitance-to-Digital Converter for Sub-μW Robust Wearable Sensing.

This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub-μW wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance (ΔC), excluding baseline and parasitic capacitances. The experimental results show the measurement range of ΔC are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 μW for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 mm2 of active area (0.0251 mm2/Ch).

A 6-9 GHz 1.28 Gbps 76 mW Amplitude and Synchronized Time Shift Keying IR-UWB CMOS Transceiver for Brain Computer Interfaces.

This paper proposes a low-power, high-speed impulse radio-ultra-wideband (IR-UWB) transceiver for brain computer interfaces (BCIs) using amplitude and synchronized time shift keying technique (ASTSK). The proposed IR-UWB transmitter (Tx) generates two pulses (sync pulse and data pulse) per symbol rate. The time difference between two pulses is used for synchronized time shift keying and the amplitude of the two pulses is used for amplitude shift keying. The receiver (Rx) demodulates the time difference with a low power time-to-digital converter (TDC) and peak detector (PD) based amplitude demodulation is suggested to relax analog-to-digital converter (ADC) burden for low power receiver. Especially the Tx-based synchronized operation eliminates the need for complex clock circuitry such as phase-lock loop (PLL) and reference crystal oscillator. Therefore, it can achieve low power and high-speed operation. The prototype, fabricated in 65 nm CMOS, has a frequency range of 6-9 GHz, communication speed of 1.28 Gbps, and power consumption of 18 mW (Tx) and 58 mW (Rx). This work is a fully integrated RF transceiver adapted for high-order modulation and designed to include the receiver.

A Wireless Multimodal Physiological Monitoring ASIC for Animal Health Monitoring Injectable Devices.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 µW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an invivo experiment.

A Fully Differential CMOS Current Memory Cell for Space-Embedded Analog-to-Digital Converters

This paper presents a radiation-hardened high-resolution current memory cell (CMC) that can be used to implement current-mode analog-to-digital converters (ADCs) for space-embedded, charge-coupled device processors. This CMC is based on a fully differential structure and on the Miller effect to reduce charge-injection errors. Using a commercial 0.35-μm 3.3-V complementary metal-oxide-semiconductor (CMOS) process, the radiation tolerance of this CMC has been enhanced by designing enclosed n-channel MOS transistors, using p-channel MOS switches only, and introducing guard rings wherever necessary. Results show that the CMC accuracy is 10 bits and that its estimated linearity error is &3x000B1;50 nA for a [-200 μA; 200 μA] dynamic input current range. Experimental results point out that signal-dependent charge injections are divided 23 times at least, which improves the CMC accuracy by approximately 4 bits. The measured acquisition time for a 200-μA input step transition to achieve a 10-bit settling accuracy is 50 ns. The active chip area and the power consumption of the proposed CMC are 0.042 mm 2 and 6 mW, respectively.

On the optimum multicarrier performance with memoryless nonlinearities

One of the major problems associated with multicarrier signals is their high envelope fluctuations that lead to implementation difficulties. Therefore, multicarrier signals are usually submitted to nonlinear operations such as clipping to simplify the power amplification, DAC (Digital-to-Analog Conversion) and other digital signal processing operations. However, these nonlinear operations lead to nonlinear noise that usually is associated with performance degradation. Recently, it was shown that the nonlinear distortion associated to bandpass memoryless nonlinear devices not only does not necessarily means performance degradation, but can even lead to performance gains. In this paper we study the impact of non-bandpass memoryless nonlinearities on the performance of multicarrier signals. We consider both nonlinear devices operating on the real-valued multicarrier signals as well as Cartesian nonlinear devices (also denoted as I-Q nonlinearities) operating separately on the real and imaginary parts of the complex envelope of multicarrier signals. We present a theoretical analysis of the potential performance improvements associated with the optimum detection of multicarrier signals, by deriving accurate theoretical expressions for both the average asymptotic gains in ideal AWGN (Additive White Gaussian Noise) channels and the asymptotic gain distribution for frequency-selective channels with multipath Rayleigh fading.

COMMUNICATION IN THE INITIAL IMPLEMENTATION OF DIGITAL TV MIGRATION IN BEKASI CITY

The migration from analog to digital television or analog switch-off (ASO) represents a solution to overcome various limitations of analog systems. Digital television offers multicasting capabilities, enabling multiple transmission signals through a single channel, thereby addressing spectrum constraints faced by analog television. This study explores communication strategies during the initial phase of analog switch-off in Bekasi City. Theoretical frameworks like diffusion of innovations highlight the importance of communication in disseminating information and facilitating technology adoption. This research uses qualitative approaches to investigate community responses and satisfaction with digital television. Findings indicate that direct information from local officials and media channels significantly influences public readiness and acceptance of digital television. The study aligns with diffusion theory stages, illustrating how knowledge acquisition, persuasion, decision-making, implementation, and confirmation phases influence community adoption. Effective communication, supported by clear regulations and governmental policies, accelerates technology adoption and enhances user satisfaction. Insights from this study underscore the importance of proactive government support and targeted communication strategies in successful ASO implementation. The findings contribute to understanding how effective communication can facilitate technology transitions and improve broadcast quality and user experience in digital television.

A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking

A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

METHODS FOR IMPROVING THE DRG-05M DOSIMETER IN BRACHYTHERAPY

Relevance: The article discusses one of the ways to improve the DRG-05M dosimeter in brachytherapy by using new components and technologies in an improved scheme, which includes more accurate sensors, advanced signal processing techniques, efficient power cells, and other solutions. The application of such advanced components and technologies in the framework of DRG-05M dosimeter modernization is a new and original contribution to the field of dosimetry. The scientific novelty of the work is the improvement of the existing circuitry, namely, the improvement of the DRG-05M dosimeter’s electrical circuitry based on the analysis of its shortcomings. This includes replacing components, optimizing circuit structure, eliminating noise and interference, and improving the stability and accuracy of measurements.&#x0D; The study aimed to improve the DRG-05M dosimeter to provide more accurate and reliable radiation measurements in brachytherapy.&#x0D; Methods: The paper analyses the existing components and their use in the electrical circuit to improve the measurement accuracy of the DRG-05M dosimeter, offers a new electrical circuit based on the collected data and requirements, considering the optimal location of components, their characteristics, performed calculations, and modeled circuit operation. This scientific research was carried out within the framework of the PCF scientific program “Metrological support of dosimetric measurements in contact radiation therapy,” IRN BR12967832.&#x0D; Results: We have selected the components for improving the DRG-05M dosimeter:photomultiplier tube (PMT), analog-digital converter (ADC), indication unit, and power supply. The proposed changes to improve the DRG-05M dosimeter shall result in a very compact scintillation-type dosimeter. Its size and weight shall be reduced by at least 3 times; the accuracy and speed of measurement will increase, and the lifetime of the instrument shall improve.&#x0D; Conclusion: Improvement of the dosimeter in brachytherapy is an important task to ensure the accuracy and reliability of measurement in treating cancer. Using components such as PMT, calibration source, battery charger, and microcontroller KR572PV5 can significantly improve the operation of the DRG-05M dosimeter and increase the accuracy of radiation dose measurement in brachytherapy.

Environmental variables monitoring system and irrigation control in a greenhouse (RIO)

The waste of water in recent years in the world has been increasing drastically, such is the case of the irrigation systems of the different crops that exist in addition to the multiple conditions where they are operating either in the open field or in a greenhouse. 70% of the water used in Mexico is destined for agriculture where 60% of this destined water is wasted by irrigation systems either by infiltration or evaporation. In Guanajuato the construction of greenhouses throughout the state is very common with different crops. The main objective of the project is to reduce the consumption of water in the irrigation systems, as well as to reduce their operating costs. To achieve the goal, an embedded system will be developed using microcontrollers, which will measure the greenhouse temperature at different points and through radio frequencies, a multipoint network will be created implementing xbee modules where the temperatures obtained will be sent to a central device which will process the information and activate irrigation automatically. To achieve this, techniques such as serial communication, analog-digital conversion, multiplexing, data analysis will be used.

Design and Characterization of Piezoresistive Sensors for Non-Planar Surfaces and Pressure Mapping: A Case Study on Kayak Paddle.

This article focuses on the design of a sensor system for a non-planar surface, in particular a cylindrical shape, such as a kayak paddle. The main objective is to develop a piezoresistive sensor system to measure the pressure exerted by the hand on the shaft. The study begins with static characterization of the sensors, including dispersion analysis to assess their sensitivity, linearity and measurement range. A calibration process is carried out using a dedicated test bench, and an inverse viscoelastic model is used to establish an accurate relationship between the measured resistance and the corresponding pressure. The sensor system is connected to a data acquisition board equipped with an analog-to-digital converter (ADC) that enables the direct conversion of analog data into digital resistance values. Furthermore, Bluetooth Low Energy (BLE) wireless communication is employed to facilitate data transfer to a computer, enabling a detailed pressure mapping of the kayak paddle and real-time data collection. The calibrated sensors are then tested and validated on the kayak paddle, facilitating the mapping of pressure zones on the paddle surface. This mapping provides information for locating areas of high pressure exertion during kayaker movements.