Analog-to-digital Research Articles

Automatic Detection of Fiber Optic Gyroscope Intrinsic Frequency Based on Optimal Projection Approximation

To address the complexity and low detection accuracy issues in the intrinsic frequency detection process of fiber optic gyroscopes, a highly precise automatic measurement method based on optimal projection approximation is proposed. Building upon the digital closed-loop fiber optic gyroscope hardware circuit, this method generates a frequency-adjustable square wave with a 25% duty cycle through field-programmable gate array (FPGA) fractional division. Subsequently, it calculates the difference between the high and low levels of the sign bits of the modulated optical intensity signal sampled by the analog-to-digital converter (ADC). This yields an error signal related to the modulation frequency and intrinsic frequency. The modulation frequency is then approximated using the nearest projection of this error signal, thereby achieving automatic detection of the fiber optic gyroscope’s intrinsic frequency. The experimental results indicate that this method, requiring no external auxiliary equipment, enables rapid and highly accurate measurement of the intrinsic frequency of the fiber optic gyroscope. The measurement of intrinsic frequency takes approximately 300 milliseconds, achieving a measurement accuracy of up to 0.001 Hz.

A novel approach for minimising anti-aliasing effects in EEG data acquisition.

Electroencephalography (EEG) waves and other biological signals can be deciphered with a deeper understanding of the human body. The benefits of EEG are growing. EEG studies have expanded globally. Research on EEG covers data gathering, analysis, energy renewal, and more. EEG-gathering devices include encoding, digital transfer, head sensor placement, and separate amplifiers. The EEG detects periodic noise. Head movement, sensor lines, and hair sweat produce low-frequency noise. Low-frequency noise alters EEG signals over time. Muscle actions and electromagnetic waves create high-frequency noise (especially in the facial and neck muscles). EEG shifts are saw-toothed by high-frequency noise. High- and low-frequency noises are usually lower and higher than human EEG, respectively. Lowering signal power above and below the testing level without altering the signs of interest lowers noise. Aliasing may affect low-frequency impacts in the original data because high-frequency noise is mirrored in the data. This work designed a non-binary Complementary metal oxide semiconductor (CMOS) Consecutive guesstimate register (CGR) reconfigurable analogue-to-digital converter (ADC) integrated with the instrumental amplifier. CGR ADC model comprises the bio-signal device monitoring for the EEG signals. This study focused on acquiring the EEG signals for amplification. The model uses the AC-coupled chopper stabilisation model with 1 A low power with a noise level of 1 A. The neural amplifier uses an optimised current technique to maximise the transconductance for a good noise efficiency factor. The simulation analysis estimates a bandwidth range of 0.05-120 Hz with a power consumption level of 0.271 µW. The computed noise level is observed as 1.1 µVrms and a gain of 45 dB. The comparative analysis of the proposed ADC model achieves the minimal energy consumption value of ∼12%, which is minimal than the nonlinear and switch-end capacitor. Also, the time consumed is ∼9% less than the nonlinear and switch-end Capacitor.18 nm CMOS technology is used to implement the proposed data acquisition system for low-power and density-optimised applications.

One-bit quantization delta-sigma modulation-based autoencoder for power-efficient free-space communication.

This Letter proposes a novel, to the best of our knowledge, approach utilizing a delta-sigma modulation (DSM)-based 1-bit autoencoder (AE) for efficient encoding and decoding in various channel conditions. Simulation analysis demonstrates the AE's ability to mitigate noise by reducing a peak-to-average power ratio (PAPR) and enhancing an in-band power of the signals, particularly under low signal-to-noise ratios (SNRs). The AE-DSM achieves theoretical transmission performance even at SNRs below 6 dB. In a 40-m free-space link experiment, the AE-DSM exhibits an 8.4-dB lower bit error rate (BER) compared to 64QAM-DSM, enabling a transmission rate of 1.31 Gbps. Furthermore, the 1-bit AE-DSM significantly reduces power consumption in the receiving analog-to-digital converter (ADC), facilitates transmission at low SNRs, and effectively mitigates nonlinear effects. Consequently, the DSM-based AE holds immense potential for future mobile fronthaul links.

A Hybrid CMOS Digital-to-Analogue Converters Design for High Resolution SAR ADC

The paper describes the design and implementation of a 14-bit differential Digital-to-Analogue Converter (DAC) based on the Silterra 0.18µm Complementary Metal-Oxide-Semiconductor (CMOS) process to be established in a Successive Approximation Register (SAR) Analogue-to-Digital Converter (ADC) for the purpose of high-resolution, high accuracy and low power applications. The proposed differential DAC aims to eliminate the issue of stringent matching requirements imposed on high-resolution DACs while leveraging both linearity performance and power consumption parameters at a balanced point. The overall differential circuit consists of two parallel single-ended DACs that utilize a 4-bit Capacitor DAC (CDAC) and 10-bit Resistor DAC (RDAC) on each end, thereby establishing a hybrid-based architecture. Furthermore, the authors illustrate the proposed switching procedures applied to the sub-DAC circuits to ensure a low-power design is established. The new method effectiveness evaluation is confirmed by detailed transient simulations implemented on the DAC where the circuit performs the required conversions at a maximum conversion frequency of 2.5 MS/s with a peak power consumption of 0.1496mW for the standard voltage supply of 2.1V. Meanwhile, the schematic and post-layout simulations performed on the DAC registers peak DNL errors of -0.1612 and -0.8272, respectively. New research results depict performance improvements in terms of resolution and power consumption which facilitates the DAC implementation in contemporary electronic devices such as microcontroller peripherals and audio amplification devices. The overall deigned circuit is capable of achieving the desired 14-bit digital-to-analogue conversions under the CMOS 0.18µm technology, proving the DAC’s high-resolution efficacy.

A 1.5 mm2 4-Channel EEG/BIOZ Acquisition ASIC With 15.2-Bit 3-Step ADC Based on a Signal-Dependent Low-Power Strategy.

This article presents a multichannel EEG/BIOZ acquisition application specific integrated circuit (ASIC) with 4 EEG channels and a BIOZ channel, a switch resistor low-pass filter (SR-LPF). Each EEG channel includes a frontend, and a 4-channel multiplexed analog-to-digital converter (ADC), while the BIOZ channel features a pseudo sine current generator and a pair of readout paths with multiplexed SR-LPF and ADC. The ASIC is designed for size and power minimization, utilizing a 3-step ADC with a novel signal-dependent low power strategy. The proposed ADC operates at a sampling rate of 1600 S/s with a resolution of 15.2 bits, occupying only 0.093 mm2. With the help of the proposed signal-dependent low-power strategy, the ADC's power dissipation drops from 32.2 μW to 26.4 μW, resulting in an 18% efficiency improvement without performance degradation. Moreover, the EEG channels deliver excellent noise performance with a NEF of 7.56 and 27.8 nV/√Hz at the expense of 0.16 mm2 per channel. In BIOZ measurement, a 5-bit programmable current source is used to generate pseudo sine injection current ranging from 0 to 22 μApp, and the detection sensitivity reaches 2.4 mΩ/√Hz. Finally, the presented multichannel EEG/BIOZ acquisition ASIC has a compact active area of 1.5 mm2 in an 180nm CMOS technology.

Power Optimization of Cell-Free Massive MIMO With Full-Duplex and Low-Resolution ADCs

This paper analyzes the spectral/energy efficiency (SE/EE) of a full-duplex (FD) cell-free (CF) massive multiple-input multiple-output (mMIMO) over Rician fading channels. Due to the FD radios, the access points (APs) suffer from self-interference (SI) and inter-AP interference (IAI) while the downlink (DL) users’ signals are corrupted by the uplink (UL) users’ transmissions. We consider the case, where low-resolution analog-to-digital converters (ADCs) are utilized at the APs and DL users, which introduces the quantization noise (QN). The combined effects of Rician κ-factor, residual SI/IAI, UL-to-DL interference, multi-user interference, and QN on the UL/DL SEs are characterized. The UL SE is degraded by the increase in DL power, whereas the growth in UL power deteriorates the DL SE. The effects of the residual SI/IAI and UL-to-DL interference are worsened by the low-resolution ADCs. We optimize the UL/DL transmit powers to maximize the overall sum SE of the network. It is observed that the proposed power allocation algorithm brings substantial sum SE gain. A trade-off analysis between the EE and SE, as a function of the ADCs’ resolution, shows that the entire envelope of the operating region of FD CF mMIMO is enhanced in Rician channels.

Performance Analysis of Cell-Free Massive MIMO Network With Large-Scale-Fading Decoding and Low-Resolution ADCs

Concentrating on cell-free massive multiple-input multiple-output (MIMO) networks with low-resolution analog-to-digital converters (ADCs), we derive the theoretical achievable uplink spectral efficiency (SE) for the minimum mean-squared error (MMSE)-based large-scale fading decoding (LSFD). Moreover, we investigate the bit allocation (BA) among access points (APs) to maximize the asymptotic sum SE under the constraint of total ADC quantization bits. Simulation results confirm that our theoretical analysis is accurate and validate that the proposed BA technique is preferable to the random and fixed counterparts.

A 14-bit 1-GS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

A 14-bit 1-GS/s Pipelined-Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 28-nm CMOS is presented in this paper. In the initial phase, a pair of SAR ADCs employing the Time-Interleaved (TI) technique are employed to attain the necessary sampling rate. A multi-comparators structure is used to increase the speed and improve the mismatch. We have implemented a foreground calibration technique to address capacitor mismatch, optimizing its processing logic to enhance the chip’s speed. The interstage operational amplifier adopts a two-stage structure. Some structural changes are presented to optimize its bandwidth and phase margin. A background calibration method for gain error is implemented. In the subsequent phase, we employ four SAR ADCs utilizing the TI method. The outcomes demonstrate that the ADC delivers a Signal-to-Noise and Distortion Ratio (SNDR) of 65.58 dB and a Spurious-Free Dynamic Range (SFDR) of 72.12 dB at a 1-GS/s sampling rate without calibration, and 69.02 dB SNDR and 81.26 dB SFDR at the same 1-GS/s sampling rate with calibration. The core layout occupies an area of 0.6 mm2 and consumes 225.02 mW of power.

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

Development and Implementation of Energy Consumer Metering System with the Integration of Smart Users’ Management Model

An electrical meter with the integration of the Internet of Things (IoT) device measures and records the consumption of electrical energy in residential and commercial buildings. This allows for remote monitoring and management of the energy usage through an IoT platform. This IoT meters emerged due to the inability of the existing metering system to smartly integrate the IoT application into the metering market. With the emergence of IoT technology, microcontrollers and sensors are deployed for this model to avert the aforementioned challenges. The microcontroller is responsible for collecting and processing data from the meter, as well as communicating with the other components of the device. The communication module enables the meter to connect to the Internet and transmit data to the cloud, to be accessed and analyzed through an IoT platform. The voltage and current sensors give input current and voltage signal for the microcontroller for analogue to digital conversion (ADC) effect as programmed. The experimental results indicate that the meter is accurate in measuring energy consumption with a maximum relative error of -6.06% as observed in Case 3 with a rated power of 40W and absolute current of 0.02A. The negative value of the relative error suggest that the measured energy is slightly lower than the actual energy consumed. The developed meter prototype engendered smart energy measurement with modern IoT technologies, this enables remote monitoring and of energy usage.

A co-simulation of superconducting qubit and control electronics for quantum computing.

As the number of qubits in quantum computing increases, the scalability of existing qubit circuit structures and control systems may become insufficient for large-scale expansion and high-fidelity control. To address this challenge, we propose a behavioral-level model of a superconducting qubit and its control electronics, followed by a co-simulation to evaluate their performance. In this paper, we present the modeling process, simulation procedure, and resulting design specifications for the qubit control system. Our co-simulation approach utilizes MATLAB and Simulink, enabling us to derive critical circuit design specifications, such as the required Digital-to-Analog Converter (DAC) resolution, which should be 8 bits or higher, to achieve high-fidelity control. By taking into account factors such as DAC sampling rates, integral and differential nonlinearities, and filter characteristics, we optimize the control system for efficient and accurate qubit manipulation. Our model and simulation approach offer a promising solution to the scalability challenges in quantum computing, providing valuable insights for the design of large-scale superconducting quantum computing systems.

An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique

This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300mV rms error.

A multi-functional arbitrary timing generator based on a digital-to-time converter.

This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time--amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal generation. Moreover, the relationship between the timing resolution and the vertical resolution and the sampling rate of DAC is discussed. Based on this, arbitrarily distributed random timing signals and editable timing signal sequence functions are realized. This method is verified in the experiment on Xilinx XCKU040 and Texas Instrument DAC37J82. Furthermore, a timing resolution of 1ps is realized. A time range of 4.2ns to 999s, an editable sequence length of 1-128k, and excellent nonlinear performance are achieved. In addition, functions for arbitrarily distributed random timing signals and signal bursts are tested. This method can be flexibly deployed on existing hardware and satisfy almost all test requirements.

Ultra-Fast and Accurate MPPT Control Structure for Mobile PV System Under Fast-Changing Atmospheric Conditions

Photovoltaic (PV) system efficiency is highly dependent on atmospheric conditions, which are continuously varying. The presence of an efficient maximum power point tracking (MPPT) method suitable for fast-changing environmental conditions, even under partial shading conditions (PSC) is required to optimize the PV system efficiency. This paper proposes a different MPPT control structure, where the MPPT is nested in the proportional-integral (PI) voltage controller routine. By using the proposed control structure. The Analog-to-Digital Converter (ADC) samples are shared between the MPPT algorithm and PI controller. As a result, extreme dynamic tracking improvements while a cost-effective implementation is ensured. Using the proposed control structure, a high-speed MPPT is achieved, making it suitable for mobile PV systems subjected to fast-changing atmospheric conditions. As the tracking accuracy is high, the P&O subroutine usually used in GMPPT methods to maintain the GMPP is eliminated. Results revealed that with the proposed implementation scheme, the tracking speed and the transient energy losses can be four times better than the traditional scheme.

Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks

Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks

Positional deviation between CBCT-based digital facebow transfer and analog facebow transfer: case series

Positional deviation between CBCT-based digital facebow transfer and analog facebow transfer: case series

A Novel Method of Digital-to-Analog Converter Combination for Precise Digital Control in Closed Loop Systems

For precise digital control applications, high-resolution feedback is essential to achieve the required performance. Precise control systems with analog input-output and digital processing are generally limited by the resolution of digital to analog converter (DAC). DACs available for space use are limited in terms of resolution and performance. This paper presents a novel approach of combining two DACs to achieve higher resolution in closed-loop control systems. DACs can be combined with an overlapping range such that nonlinearity of higher significant DAC does not cause oscillations and instability when lower significant DAC rolls over. Flowchart of the algorithm for combining two DACs is presented, along with a detailed analysis. Simulation results are also shown elaborating the behaviour of DACs in non-overlapping and overlapping combination methods. The non-overlapping combination may result in oscillations, while the overlapping combination can settle the loop after a small settling time. An implementation example of a digital lock-in amplifier for the Rubidium atomic clock, showing the realization of a coarse-fine DAC combination to achieve 20-bits resolution with two 12-bits DACs, is also presented. This approach will result in achieving better performance in small-bandwidth digital control systems.

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

Development of the digital multichannel analyzer for liquid scintillation detection

The new digital multichannel analyzer (DMCA) based on field programmable gate array (FPGA) technology is successfully developed, and it is used for liquid scintillation detection. The performance of this system has been evaluated. The analog signal output emanating from the photomultiplier tube (PMT) is transformed into digital signals through the utilization of an amplifier and a high-speed analog-to-digital converter (ADC). Information about the energy, timing, and pulse shape characteristics of the radiation event is contained in the digital signal. Subsequently, this digital signal is directed towards the FPGA for digital signal processing. In order to reduce the thermal and electronic noise, the dual-channels configuration and the signal coincidence function are added to DMCA for optimizing the validity of signal. The signal coincidence unit is designed within the FPGA, optimizing the synchronization of signals. The measurement data is transmitted to a computer via USB interface. The energy spectra of gamma sources, namely 22Na, 60Co, and 137Cs, as well as the alpha source 232Th, were measured utilizing the newly developed system. Notably, thermal and electronic noise interference is reduced in the coincidence measurement mode, and the coincidence energy spectra are improved compared to the singles measurement. In contrast to commercially available systems, the advantages of our design in terms of miniaturization, cost-effectiveness, and expandability are demonstrated.

Experimental demonstration of the quantum noise randomized cipher based on cascaded phase shift keying without a high-level digital-to-analog converter.

To break the dependence on a high-speed and high-resolution digital-to-analog converter (DAC) in the traditional quantum noise randomized cipher (QNRC), a practical DAC-free modulation scheme based on cascaded phase-shift keying (PSK) is proposed and demonstrated by a proof-of-concept experiment. By employing seven cascaded phase modulators (PMs) driven by designed electrical voltage signals, a 128PSK-QNRC system is achieved with a transmission rate of 10Gbaud/s and a transmission distance more than 50km, which eliminates the need for a DAC on the transmitter side. The bit error rate (BER) performance of the proposed scheme is compared to that of a traditional scheme based on an arbitrary waveform generator (AWG) with a sampling rate of 25GSa/s. The results show that compared to a traditional scheme, the power penalties of the proposed scheme are -1.8d B, 0.9dB, and 1dB, respectively, at the rates of 10, 5, and 2.5Gbps. In other words, the BER performance of the proposed scheme is close to the traditional scheme at a low transmission rate, but better than that of the traditional scheme at a high transmission rate, where the sampling rate of the DAC is not high enough to generate a complete waveform. This work greatly enhances the security of a QNRC system.