Si Active Layer Research Articles

Electrical Characterization of Silicon-on-Insulator Wafers Using Photo-Conductance Decay (PCD) Method

In this work the photo-conductance decay (PCD) technique is used to measure the effective carrier lifetime in 160 nm–180 nm thick active layers of silicon-on-insulator (SOI) substrates both SIMOX and bonded. Study was carried out using 405 nm excitation wavelength featuring 200 nm absorption depth in silicon which was selected to coincide with the thickness of the active layers in the SOI wafers studied. The results obtained indicate the effectiveness of PCD methodology adopted for this study in the measurements of the minority carrier lifetime in Si active layers in SOI substrates. They demonstrate differences between PCD characterization of bulk and SOI wafers which are related to the confinement of the depletion region within the Si active layer in the latter case making its electrical properties less sensitive to the variation of the surface chemical condition. On the other hand, the process related physical changes in the SOI surface morphology were readily detectable by PCD measurements. Furthermore, the specific outcome of this investigation is the result indicating higher minority carrier lifetime in the Si active layer of bonded SOI wafers as compared to SIMOX wafers used in this study.

Optimization of the Antireflection Coating of Thin Epitaxial Crystalline Silicon Solar Cells

In this work we use an effective weighting function to include the internal quantum efficiency (IQE) and the effective thickness, Te, of the active cell layer in the optical modeling of the antireflection coating (ARC) of very thin crystalline silicon solar cells. The spectrum transmitted through the ARC is hence optimized for efficient use in the given cell structure and the solar cell performance can be improved. For a 2-μm thick crystalline silicon heterojunction solar cell the optimal thickness of the Indium Tin Oxide (ITO) ARC is reduced by ∼8nm when IQE data and effective thickness are taken into account compared to the standard ARC optimization, using the AM1.5 spectrum only. The reduced ARC thickness will shift the reflectance minima towards shorter wavelengths and hence better match the absorption of very thin cells, where the short wavelength range of the spectrum is relatively more important than the long, weakly absorbed wavelengths. For this cell, we find that the optimal thickness of the ITO starts at 63nm for very thin (1μm) active Si layer and then increase with increasing Te until it saturates at 71nm for Te > 30μm.

Annealing Effects on the Electrical Activation of Si Dopants in InGaAs

There is a renewed interest in integrating high mobility III-V channel materials into sub 10 nm nMOS devices but the continued scaling of devices has resulted in the need to create contacts and source/drains with ultra low contact resistivities in order to reduce current losses. This study investigates thermal stability of Si dopants incorporated via MBE growth and ion implantation as potential methods to create heavily-doped, low resistance source/drain regions in III-V channel devices. For this study, the electrical activation and diffusion of Si active layers in In0.53Ga0.47As formed by a 10 keV, 5×1014 cm-2 Si implant and MBE growth doping with a peak Si concentration of 7×1019 cm-3 were investigated as a function of post growth and post-implant isochronal annealing. While most previous studies conclude that MBE doping can achieve higher active Si concentrations than ion implantation, the results of this study show conclusively that electrically active Si concentrations above 1.4×1019 cm-3 formed by MBE doping are prone to deactivation upon thermal treatment after growth whereas ion-implantation shows no metastable activation behavior. Significant Si deactivation in MBE doped substrates is shown to occur before the onset of Si diffusion whereas saturated activation in ion implanted substrates does not occur until diffusion is observed. Upon annealing at sufficiently high temperatures to cause Si diffusion, the electrical activation of Si in MBE doped substrates and ion implanted Si are shown to converge to a stable activation limit of 1.4×1019 cm-3. The common activation limit upon Si profile motion for both Ion implanted and growth doped Si active layers after thermal annealing at 750°C suggests that the maximum stable electrical activation of Si is an intrinsic property of In0.53Ga0.47As. Si diffusivity has also been calculated from SIMS results in both ion-implanted substrates and growth-doped substrate and Si diffusion in MBE doped substrates was observed to be nearly three times as fast as ion implanted substrates presumably due to the observed concentration dependent diffusion effects. The mechanism of Si diffusion and its relation to the observed concentration dependent diffusion and electrical activation behavior in both materials are also discussed. Figure 1

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

A new high-voltage LDMOS with folded drift region (FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Siactive layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.

Plasmonic-enhanced Si Schottky barrier solar cells

By introducing silver nanoparticles (NPs) and SiO2 spacer layers on top of Si-based Schottky barrier solar cells, we demonstrated a positive and tunable light trapping effect introduced by metallic NPs. A redshift of the surface plasmon resonant wavelength of Ag NPs from 550nm to 650nm, corresponding to the optical absorption peak of the solar cell, was observed with an increased average particle diameter from 19.7nm to 85nm. Enhanced light trapping effects at distinct resonance wavelengths were observed in the optical spectra of the plasmonic-enhanced devices. Electrical measurements confirmed the expected photocurrent improvement at these corresponding wavelengths. It was also revealed that the Ag NPs enhance the carrier generation rate inside of the Si active layer without sacrificing carrier collection efficiency of the device. The short-circuit current density of the best cell we obtained in this work was improved from 13.7mA/cm2 to 19.7mA/cm2, with an enhancement factor of 43.7%.

Heteroepitaxial reflector for the fabrication of Si thin film photovoltaic devices

Thin film crystalline Si diodes are a viable solution to the goal of fabricating economical photovoltaic (PV) cells. A functional, light trapping, thin film PV was fabricated with a heteroepitaxial (YSZ) reflecting layer which also served as a complaint layer for the growth of crystalline Si or SiGe active layers. X-ray analysis confirmed that the deposited semiconductor layers were crystalline. It was observed that the light trapping PV cell formed with the YSZ reflector layer increased the short circuit current under illumination by 22% over that fabricated without the YSZ reflector layer. It was further observed that the surface texture in the YSZ layer contributed to both the ability to grow crystalline semiconductor layers and to act as an effective light trapping structure.

Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

This paper reports a simulation study investigating the drive current of a prototypical SiGe n-type FinFET built on a relaxed SiGe substrate for different values of the Ge content <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> in the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(1-</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> )Ge <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> active layer. To this purpose, we performed strain simulations, band-structure calculations, and multisubband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering.

(Invited) 3D Integration in Silicon Technology

3Di (3D integration) refers to a family of technologies which enable the stacking of active Si layers with vertical connections between them. 3Di has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. Several researchers have investigated TSV (Through Silicon Via) fabrication, insulation, metallization, integration, the impact of TSVs on devices, thermo-mechanical integrity and reliability of TSVs. This paper presents a review of some of these publications in order to understand the options and challenges in 3Di.

200 mm Silicon On Porous Layer Substrates Made by the Smart Cut Technology for Double Layer-Transfer Applications

Silicon On Porous Layer (SOPL) substrate was fabricated by applying the Smart Cut technology to silicon substrate having a superficial porous Si layer. It consists in a non-porous/porous single crystalline Si bilayer transferred onto a handling wafer to form Silicon-On-Insulator (SOI) like structure. Subsequent bonding to a final wafer and separation induced in the fragile embedded porous Si layer led to the double transfer of the single crystalline non porous Si layer. Changes in structural and mechanical properties of the embedded porous silicon layer as a function of the annealing temperature were also determined. Thickness homogeneity of the transferred thin Si layer was estimated after SOPL fabrication and after double layer-transfer achievement. The perfect crystallinity of the active Si layer was conserved during the whole process. SOI-like structure fabrication and subsequent separation of thin high quality Si film are reported in order to demonstrate capability of SOPL structure with double-sided layer processing for device integration.

Nanometer resolution stress measurement of the Si gate using illumination–collection-typescanning near-field Raman spectroscopy with a completely metal-inside-coated pyramidalprobe

We have proposed an illumination–collection-type scanning near-field Ramanspectroscopy (SNRS) with a completely gold metal-inside-coated (MIC) pyramidalprobe without an optical aperture in order to detect the Raman spectra of fine Sidevices for local stress measurements. The gold MIC pyramidal probe has beenstudied to act as a plasmon resonance near-field optical probe with high powerusing a finite differential time domain (FDTD) simulation and the prototypedSNRS. In the simulation, the propagated optical power can be made available forSNRS. In the experiments, it is clear that the prototyped SNRS enhanced the SiRaman peak signal by plasmon resonance and could measure the Si Raman peakshift by line scanning the Si gate region and the Si active layer. Furthermore,compressive and tensile stresses localized around the Si gate were demonstrated by theSi Raman peak shift with a resolution of about 10 nm. It is clarified that theproposed SNRS has the possibility of detecting the Raman spectra of a local area.

200 mm Silicon on Porous Layer Substrates Made by the Smart Cut Technology for Double Layer Transfer Applications

Silicon On Porous Layer (SOPL) substrate was elaborated by applying the Smart Cut{trade mark, serif} technology to silicon substrate having a superficial porous Si layer. Porous Si layer morphology was characterized after anodisation process. A single crystalline/porous Si bilayer was transferred onto a handling wafer to form SOI like structure. Subsequent bonding to a final wafer and separation induced in the fragile embedded porous Si layer led to the double-transfer of the single crystalline Si layer. Changes in mechanical properties and chemical composition of the embedded porous silicon layer as a function of the annealing temperature were also determined. Thickness homogeneity of the transferred thin Si layer was estimated after SOPL fabrication and after double-transfer achievement. The perfect crystallinity of the active Si layer was conserved during the whole process. SOI-like structure fabrication and subsequent separation of thin high quality Si film are reported in order to demonstrate adequacy of SOPL with post device post processing substrate removal.

Imprinting a needle array on a polycarbonate substrate

A micro-needle array was fabricated on a polycarbonate (PC) substrate using an electroformed-Ni mold with a conical concave pattern. The diameter and length of each needle were 50 μm and 135 μm, respectively. The needle array pattern of the electroformed-Ni mold was produced by combining a grayscale mask for X-ray lithography with Ni electroforming technology. The X-ray grayscale mask was composed of Si absorbers and a SU-8 membrane. Each Si absorber had a three-dimensional cone shape rather than a rectangular shape. Threedimensional Si structures were formed to etch an active Si layer in a silicon-on-insulator wafer using a taperedtrench etching technology. Beamline BL-4 in the TERAS synchrotron radiation facility at AIST was used for the Xray lithography experiments. X-rays that penetrated the X-ray grayscale mask irradiated a polymethylmethacrylate (PMMA) sheet. Pt was deposited on the PMMA structure after developing, and Ni was electroformed on it. The electroformed-Ni object was processed by grinding to complete a Ni mold. Finally, the micro-needle array was fabricated by thermal-imprinting on a 0.5-mm thick PC sheet with the electroformed Ni mold.

Hydrogenated amorphous and nanocrystalline silicon solar cells deposited by HWCVD and RF-PECVD on plastic substrates at 150 °C

In this work we present a study of the structural, optoelectronic and transport properties of a series of Si films deposited in a parameter region (namely hydrogen dilution) corresponding to a transition from amorphous-to-nanocrystalline silicon by hot-wire (HW) and radio-frequency plasma enhanced chemical vapor deposition (RF) on plastic substrates at 150°C. To achieve a higher deposition rate of Si films by RF we used a relatively high power density (350mW/cm2) and deposition pressure (1.5Torr). For certain hydrogen dilution values, these deposition conditions can lead to the formation of Si crystals in the silane plasma and to a growth of polymorphous silicon film. This material has improved carrier transport properties (ambipolar diffusion length=220nm) and very high photosensitivity (>5×106). The best HW amorphous silicon films exhibited lower photosensitivity (7×104) and an ambipolar diffusion length of only 100nm. For solar cell fabrication, we optimized the RF deposition conditions to produce very thin amorphous and nanocrystalline phosphorous and boron doped silicon layers. Our best n–i–p solar cell, with a polymorphous Si intrinsic layer deposited on plastic, has an efficiency of 5.5%, FF=52.5%, VOC=920mV, JSC=11.6mA/cm2. For solar cells with a nanocrystalline Si active layer deposited on glass the following results were achieved: efficiency=3.4%, FF=43.5%, VOC=460mV, JSC=17.2mA/cm2; and on plastic substrate: efficiency=2.2%, FF=32.7%, VOC=397mV, JSC=17.2mA/cm2.

Silicon metal-semiconductor–metal photodetector with zinc oxide transparent conducting electrodes

Transparent conducting oxides thin layers, due to their optical and electrical properties, can be used as transparent electrodes in various optoelectronic devices. We present a metal-semiconductor–metal photodiode (MSM-PD) on silicon as optically active layer with zinc oxide (ZnO) thin layer as interdigitated Schottky transparent electrodes. The advantage of using a ZnO thin layer as Schottky electrodes consists in the improvement of the photoresponse by eliminating the shadowing of the active area by opaque metallic electrodes. ZnO thin layers were deposited on 10 Ω cm resistivity silicon epitaxial wafers by the vacuum thermal evaporation method. High purity metallic powders were mixed with an (Al+Sn)/Zn ratio of 0.03. In order to obtain transparent layers the metallic depositions were thermally treated at 450 °C for 2 h. The Al, Sn co-doped ZnO layers of 0.5–0.8 μm were investigated regarding structural, optical and electrical properties and surface morphology. The obtained thin layers have a high transparency (T>85%) over a large spectral range and the resistivity is quite low, ρ~10−4 Ω cm. The interdigitated Schottky contacts of ZnO were configurated onto the optically active Si layer providing an MSM-PD structure of 0.143 mm2 active area and finger spacing and finger width of 6 μm. The optoelectronic characteristics were measured and the Schottky barrier height of 0.62 eV was determined from the current–voltage characteristic. A responsivity of 0.2 A/W at 475 nm and a capacitance of 1.4 pF at 10 V bias were obtained for the MSM-PD structure with transparent conducting ZnO Schottky electrodes.

PERFORMANCE LIMITATIONS OF Si CMOS AND ALTERNATIVES FOR NANOELECTRONICS

It is believed that below the 65-nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge , high-k gate dielectrics and metal gate electrodes. Continuous scaling of VLSI circuits can pose significant problems for interconnects. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu . As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. We focus on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiple active Si layers. Heterogeneous integration of the new structures and materials on Si may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.

P-17: High Performance Polycrystalline Silicon TFTs by Heat-Retaining Enhanced Crystallization for SOP and AMOLED Applications

For the purpose of a reliable driving back-plane in AMOLED application, the Heat Retaining Enhanced Crystallization (HREC) technology is developed. A heat-retaining capping layer is applied in order to effectually slow down the heat dissipation and to retain the duration of melt, hence an enlarged poly-si grain lateral growth is obtained. With single-shot laser irradiation, a 7um-well location-controlled-n ploy Si active layer is obtained, exhibiting a high mobility (uFE=260cm2/Vsec) for the proposed dual-gate TFT device.

Modeling Study of the Impact of Surface Roughness on Silicon and Germanium UTB MOSFETs

We outlined a simple model to account for the surface roughness (SR)-induced enhanced threshold voltage (V/sub TH/) shifts that were recently observed in ultrathin-body MOSFETs fabricated on <100> Si surface. The phenomena of enhanced V/sub TH/ shifts can be modeled by accounting for the fluctuation of quantization energy in the ultrathin body (UTB) MOSFETs due to SR up to a second-order approximation. Our model is then used to examine the enhanced V/sub TH/ shift phenomena in other novel surface orientations for Si and Ge and its impact on gate workfunction design. We also performed a calculation of the SR-limited hole mobility (/spl mu//sub H,SR/) of p-MOSFETs with an ultrathin Si and Ge active layer thickness, T/sub Body/<10 nm. Calculation of the electronic band structures is done within the effective mass framework via the Luttinger Kohn Hamiltonian, and the mobility is calculated using an isotropic approximation for the relaxation time calculation, while retaining the full anisotropy of the valence subband structure. For both Si and Ge, the dependence of /spl mu//sub H,SR/ on the surface orientation, channel orientation, and T/sub Body/ are explored. It was found that a <110> surface yields the highest /spl mu//sub H,SR/. The increasing quantization mass m/sub z/ for <110> surface renders its /spl mu//sub H,SR/ less susceptible with the decrease of T/sub Body/. In contrast, <100> surface exhibits smallest /spl mu//sub H,SR/ due to its smallest m/sub z/. The SR parameters, i.e. autocorrelation length (L) and root-mean-square (/spl Delta//sub rms/) used in this paper is obtained from the available experimental result of Si<100> UTB MOSFETs, by adjusting these SR parameters to obtain a theoretical fit with experimental data on SR-limited mobility and V/sub TH/ shifts. This set of SR parameters is then employed for all orientations of both Si and Ge devices.

Fabrication and thermal evaluation of silicon on diamond wafers

Silicon on diamond (SOD) is proposed as a superior alternative to conventional silicon on insulator (SOI) technology for silicon-based electronics. In this paper, we present a novel SOD structure in which the active Si layer is in direct contact with a thick, highly oriented diamond (HOD) layer that is directly attached to a heat sink. In contrast to the earlier work,1,2 the diamond film is relatively thick (∼70 µm), free standing, and close to single crystalline, thus possessing much greater thermal conductivity and no limitation of the Si backing wafer. Two different fabrication schemes are investigated: (1) direct growth, where the Si-device layer makes contact with the nucleation side of the diamond layer; and (2) wafer fusion, where the Si device layer makes a direct contact with the diamond growth surface. Thermal evaluation was performed using metallic microheaters. These studies clearly showed more than one order of magnitude better thermal management properties of diamond with respect to Si and SOI.

Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress

Smart power SOI technology electrostatic discharge (ESD) protection devices are investigated under the transmission line pulser (TLP) and very-fast TLP stress. Thermal and free carrier distributions in the Si active layer during the stress are measured by transient interferometric mapping (TIM) method. It is shown that in contrast to measurements in bulk structures, the TIM phase signal in SOI structures is affected by multiple reflections within the Si active layer. The influence of the thickness of the Si active and oxide layers on the phase signal is investigated by optical matrix simulation. The triggering homogeneity, hot spots and carrier injection places are analysed in devices with a circular and linear geometry and correlated with results of device simulation.

Microelectron field emitter array with focus lenses for multielectron beam lithography based on silicon on insulator wafer

We report on a device concept, results of fabrication, and characterization of a monolithic electron field emitter array with focus lenses for multielectron beam lithography and high-density nano data storage. An array of individually addressable emitters of various materials was patterned on oxidized etch pits of a silicon on insulator (SOI) wafer. Si active layer of the SOI with gate hole array that self-aligned with the emitters was used as a common gate electrode. An array of cylindrical holes formed at the Si base of the SOI was used as a common lens electrode. For a single Pt emitter with gate hole of 2 μm diameter, the emission current started at a gate voltage Vgate=90 V and reached to 1.2 μA current and 0.84 mW beam power at Vgate=300 V and anode voltage Vanod=0.7 kV. The emission current was found to be stable with a fluctuation smaller than 10%/h. The emitter-gate and emitter-lens leak currents were found to be less then 1% compared with the emission current. The focusing characteristic of the device was experimentally confirmed by observing emission patterns on a phosphor anode screen. A simulation work using a finite-element method has shown that the emitted electron beam with emission cone angle within 15° can be focused at a spot of 40 nm diameter and 200 μm focal length at a lens voltage Vlens=−6 V.