Accurate Circuit Simulation Research Articles

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

Computation of period sensitivity functions for the simulation of phase noise in oscillators

Accurate phase noise simulation of circuits for radio frequency applications is of great importance during the design and development of wireless communication systems. In this paper, we present an approach based on the Floquet theory for the analysis and numerical computation of phase noise that solves some drawbacks implicitly present in previously proposed algorithms. In particular, we present an approach that computes the perturbation projection vector directly from the Jacobian matrix of the shooting method adopted to compute the steady-state solution. Further, we address some problems that arise when dealing with circuits whose modeling equations do not satisfy the Lipschitz condition at least from the numerical point of view. Frequency-domain aspects of phase noise analysis are also considered and, finally, simulation results for some benchmark circuits are presented.

A precision physical model for three terminal diffused or ion-implanted resistors

In modern CMOS and BiCMOS technologies, the diffused or ion-implanted resistors are widely used devices. One important source of errors in the accurate analog circuit simulation is the variation of resistance respect to applied voltage for diffused or ion-implanted resistors. This paper analyzes the electrical properties of the diffused resistors, and derives a closed form precision physical model for three terminal diffused resistors or ion-implanted. The voltage dependency of the resistance can be described by the depletion layer spreading into the resistor body. The back bias effect is also included in the model. The temperature model is derived from the mobility and built-in potential temperature models. The extreme cases have been studied, which sets up the minimum resistor width and maximum applied voltage of diffused or ion-implanted resistors. Good match between the modeled and experimental results is observed in the diffused resistors with n- and p-type doping.

Circuit Modeling of 3-D Parallel-plate Capacitors Fabricated by LTCC Process

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

Above-threshold parameter extraction and modeling for amorphous silicon thin-film transistors

This paper presents modeling and parameter extraction of the above-threshold characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) in both linear and saturation regions of operation. A bias- and geometry-independent definition for field effect mobility considering the ratio of free-to-trapped carriers is introduced, which conveys the properties of the active semiconducting layer. A method for extraction of model parameters such as threshold voltage, effective mobility, band-tail slope, and contact resistance from the measurement results is presented. This not only provides insight to the device properties, which are highly fabrication-dependent, but also enables accurate and reliable TFT circuit simulation. The techniques presented here form the basis for extraction of physical parameters for other TFTs with similar gap properties, such as organic and polymer TFTs.

Simulation Models for Robust Design Using Location Depth Methods

AbstractFor a cost‐effective production of integrated circuits, one important aspect is the accurate simulation of electronic circuits with regard to process variation. Process variation is described as the range of simulation (SPICE) parameters, but to reduce the costs of simulation they are replaced by easily available e‐test parameters. An approximate algorithm for the location depth (multivariate ranking) selects all data points with location depth less than or equal to one as boundary points for the multidimensional data set of e‐test parameters. The corresponding SPICE parameter values are simply obtained by linear mapping. To increase the robustness of the simulation the region covered by the set of boundary points is extended by determining the point with the deepest location (multivariate median) and adding to each boundary vector a fixed portion of the vector from the median to the boundary vector. This natural extension also covers moderate process shifts without changing the covariance structure of the data. These methods are integrated into an automated generation flow to be applicable in a production and circuit design environment. The statistical methods are validated by simulation experiments of typical analog/mixed‐signal circuit designs. Copyright © 2003 John Wiley & Sons, Ltd.

Design of asymmetrical rf and microwave bandpass filters by computer optimization

This paper presents an optimization-based approach to the design of asymmetrical filter structures having the maximum number of return- or insertion-loss ripples in the passband such as those based upon Chebyshev function prototypes. The proposed approach has the following advantages over the general purpose optimization techniques adopted previously such as: less frequency sampling is required, optimization is carried out with respect to the Chebyshev (or minimax) criterion, the problem of local minima does not arise, and optimization is usually only required for the passband. When implemented around an accurate circuit simulation, the method can be used to include all the effects of discontinuities, junctions, fringing, etc. to reduce the amount of tuning required in the final filter. The design of asymmetrical ridged-waveguide bandpass filters is considered as an example. Measurements on a fabricated filter confirm the accuracy of the design procedure.

Fast on-chip inductance simulation using a precorrected-FFT method

In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. The grid representation enables the use of the discrete FFT for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121 000 inductors and over 7 billion mutual inductive couplings in about 20 min. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block-diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.

A compact large signal model of LDMOS

Lateral double-diffused MOSFETs (LDMOS) are becoming more popular in RF power amplifiers for wireless communication applications. The understanding of non-linearity in LDMOS is critical in order to design ultra-linear power amplifiers to meet the stringent needs of current wireless systems. We have developed a compact large signal model that can predict accurately the transconductance of the device and its higher order derivatives. Such large signal model is needed in the accurate simulation of non-linear circuits. Our device measurements show that the higher order derivatives of the transconductance are very sensitive to the gate bias. The model has been applied to simulate the gain and third order intermodulation distortion in a RF LDMOS amplifier, and the simulated results agree well with the experimental measurements.

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.

MOSFET MODELING AND PARAMETER EXTRACTION FOR RF IC'S

After reviewing the basic concept and general strategies, we have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation is also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal I-V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET is very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach is examined with various examples.

Equivalent-circuit modeling and verification of metal-ceramic packages for RF and microwave power transistors

A modeling procedure was developed to generate electrical package models for metal-ceramic packages. These models are capable of accounting for package effects associated with the package lead capacitance, the self and mutual inductances of the bond wires, and the coupling between the input and output of the package. A combination of full-wave electromagnetic simulation and equivalent-circuit model extraction allows accurate model generation and efficient circuit simulation. Measured S-parameters were used to verify the overall modeling methodology. It has been demonstrated that the package effects play an important role in the accurate prediction of the packaged transistor performance.

Structure related beam propagation

The general theory of a class of structure related (SR) non-orthogonal coordinate systems is introduced for the first time. Special cases of this type of coordinate system used separately or in combination can automatically follow the local geometry of many common optical waveguide designs, thereby facilitating the fast and accurate simulation of photonic circuits, when incorporated within a FD-BPM algorithm. Substantial savings in run time and memory are possible in comparison with standard FD-BPM in rectangular coordinates.

Observation of "capacitance overshoot" in the transient current measurement of polysilicon TFT's

We have observed and analyzed a new effect in the transient current measurement of polysilicon TFT's: the presence of an "overshoot" in the transient response, which implies a time dependent gate capacitance exceeding C/sub ox/ WL. We have also performed two-dimensional (2-D) transient simulations to explain the experimental results. Our analysis indicates that a TFT circuit model based on lumped intranodal impedances cannot explain the observed transient current behavior. It follows that the "subtransistor" approach is essential for accurate dynamic circuit simulations.

A novel analytical model for short channel heterostructure field effect transistors

In this paper, we propose a novel analytical model for accurate and efficient simulation of integrated circuits with short channel heterostructure field effect transistors (HFETs). The proposed model for short channel HFETs is based on an analytical expression of the voltage-dependent two-dimensional electron gas density, which is either a linear or logarithmic function of the gate voltage. This compact model accurately describes the electrical characteristics of HFETs over the whole operation range including linear, saturation, and subthreshold operation without any discontinuity, which is known to be a detrimental factor for accurate modeling and simulation of analog and digital integrated circuits with field effect transistors. This new compact model has been verified with experimental data obtained from an Al 0.3Ga 0.7As/GaAs/In 0.13Ga 0.87As double heterojunction pseudomorphic HFET with a gate length L g=1 μm.

A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays.

Interconnect and substrate modeling and analysis: an overview

Accurate models for on-chip metal interconnect, silicon substrate, and packaging have become necessary for accurate simulation of high-performance ULSI circuits and high-speed RF designs. An overview of the hierarchy of techniques used to model and simulate these structures is given. While not an exhaustive summary, the purpose of the paper is to give the designer fundamental and practical understanding of principles used in modeling and analysis. The range of techniques from three-dimensional (3-D) modeling to quasi-3-D to transmission lines are analyzed, and their importance and impact are described. A modeling strategy that can include various kinds of modeling techniques and nonlinear devices in one simulation is also described.

MOS transistor modeling for low-voltage and low-power analog IC design

This paper covers the device modeling aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. The influence of low-current biasing on noise and matching are also discussed. The design process has to be supported by efficient and accurate circuit simulations. To this end, the EKV compact MOST model for circuit simulation is shortly presented.

A new modeling technique for mixed-mode simulation of CMOS circuits

An efficient and accurate simulation of digital circuits is of utmost importance in VLSI design to correctly predict timing performance and to accurately predict electrical waveform at all the nodes which link to analog blocks. To achieve this objective, an improved technique to correctly model the conductance of MOS device for electrical logic simulation (ELogic) of CMOS circuits is proposed [7]. The technique is general and applicable to any integrable analytic device current model. The model is implemented in a well-known mixed-mode simulator iSPLICE3. The examples show that the improved technique is able to correctly predict several complete electrical waveforms with a large voltage step of 1 V with only five logic levels to yield at least an order of magnitude computational time advantage over the circuit simulation with virtually minimal loss in the accuracy.

Mixed Analog Digital Simulation of Integrated Circuitswith BRASIL

In this paper the approach of BRASIL in modelling digital integrated circuits is presented. BRASIL consists of a timing simulator for digital MOS circuits coupled with an algorithm for circuit simulation. The timing simulation is based upon a fast macromodelling approach and the calculation of time-variant RC networks. The circuit simulator takes advantage of structuring the system of nodal equations. With BRASIL a fast and accurate simulation of digital circuits, with special regard to the analog behaviour of highly integrated systems is possible.