Accurate Compact Model Research Articles

An Improved Compact Model for a Silicon-Carbide MOSFET and Its Application to Accurate Circuit Simulation

This paper presents an improved compact model for a discrete silicon-carbide (SiC) MOSFET . This compact model based on the previous model features a new behavioral model of output characteristics and new nonlinear models of internal capacitors. Simulation with the improved compact model is in better agreement with measurement than that with the previous compact model, as well as transient behavior of the drain–source voltage, the drain current, and the leakage current out of a heatsink. Furthermore, the improved model is useful for constructing the accurate compact model that can reproduce the high-frequency characteristics of the transient waveforms of SiC- MOSFET s. This successful validation indicates that the improved compact model would be a promising tool for a full-simulation-based design system of the power converters using SiC- MOSFET s.

An accurate compact model to extract the important physical parameters of an experimental nanoscale short-channel SOI MOSFET

A new compact model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) analytically. The effective physical parameters of the experimental nanoscale SOI MOSFET were successfully extracted for the first time using an efficient search algorithm named particle swarm optimization (PSO) as a link between the analytical drain model and the experimental data. Seven important parameters, viz. the drain-induced barrier lowering, subthreshold swing, additional resistance at the source terminal, carrier velocity, low-field carrier mobility, and threshold voltage, were sought using the PSO algorithm to obtain the best fitness value. The results revealed that the application of this PSO strategy achieved an excellent match between the proposed drain current model and experimental data notwithstanding the initial values of the fitting parameters. Also, the internal node capacitances of the short-channel SOI MOSFET were successfully extracted for use in compact models of its small-signal operation.

Continuous Compact Model of a SiC VDMOSFET Based on Surface Potential Theory

Fast and accurate compact models of Silicon Carbide (SiC) power semiconductors are necessary for the development and optimization of SiC power integrated circuits. This paper presents a new physics based compact model for vertical SiC MOSFETs. The proposed model is able to accurately simulate device characteristics by iteratively calculating the surface potential under consideration of important material and geometry effects.

Modeling a Double-Halo-Doping Carbon Nanotube FET in DC and AC Operations

Double-Halo-Doping carbon nanotube field effect transistor (DH-CNTFET) has been recently suggested as a reliable and efficient device for the nanoscale applications which is a potential candidate to obsolete the conventional CNTFET (C-CNTFET), eventually. In this respect, the work aims to present an accurate compact analytical model for the drain current which is applicable in the different SPICE levels for circuit simulations. The paper captures the fundamental physic of a conventional CNTFET in order to develop a comprehensive and accurate analytical drain current model for the DH-CNTFET structure. Regarding the DH-CNTFET structure, important decision variables in the cases of ballistic carrier velocity, electron mobility, source/drain series resistance, threshold voltage, drain induced barrier lowering (DIBL) factor, fermi level to the band edge in the source region, subthreshold swing factor and band-to-band tunneling factor are introduced and globally searched by the PSO algorithm to achieve the most accurate relation for the drain current. The suggested compact analytical model is successfully compared with the realistic data extracted from the numerical simulation of the DH-CNTFET by full quantum mechanical Green's function approach. The results revealed that the compact analytical model predicts the drain current of the DH-CNTFET, accurately. As the other worthwhile effort, the work has proposed a compact analytical model for the gate-source and gate-drain capacitances providing it very attractive and suitable for the simulations under the circuit in the SPICE different levels.

A Versatile and Accurate Compact Model of Memristor With Equivalent Resistor Topology

Memristor appeals to a wide research field as the fourth passive element, and its model has been a necessary topic for future circuit applications. In this letter, a novel compact model of memristor, based on the equivalent resistor topology of variable conductive filaments, is presented. Since the formation and annihilation of conductive filaments is a natural mechanism of mainstream memristor, the model is essential and so more accurate than those nonlinear dopant drift models. On the other hand, the equivalent resistor idea makes our model versatile and efficient comparing with some complex physical process methods, and fulfills the requirements of circuit design. The versatility and accuracy of our compact model have been verified by the results that it can reduce at least 30% error in a Pt/TiO2/TiO2+ x /Pt type memristor and at least 20% error in a Ta/TaO x /Pt type memristor, comparing with some popular models. Moreover it is easier to be implemented in Verilog-A, which possesses more flexibility and higher applicability in circuit design.

Comprehensive vertical-cavity surface-emitting laser model for optical interconnect transceiver circuit design

Directly modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in short-reach optical interconnect applications. To enable efficient optical interconnect transceiver systems operating at data rates up to 25 Gb/s and beyond, cosimulation environments, which allow for the optimization of driver circuitry with accurate compact VCSEL models, are necessary. A comprehensive VCSEL model, which captures thermally dependent electrical and optical dynamics and provides direct current, small-, and large-signal simulation capabilities with self-consistency, is presented. The device’s electrical behavior is described with an equivalent circuit, which captures both large-signal operation and electrical parasitics, while the optical response is captured with a rate-equation-based model. Bias and temperature dependencies are incorporated into both key electrical and optical model parameters. Experimental verification of the model is performed at 25 Gb/s with a 990-nm VCSEL to study the impact of bias current level and substrate temperature.

A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization

A physics-based simple and accurate compact model of drain current for GaN-based high electron mobility transistors (HEMTs) is presented. The model is developed using analytical relations for charges in the 2-D electron gas and barrier layer. For the first time, a simple charge linearization approach has been used for GaN-based HEMTs. The access regions are accurately modeled using transistors. The model is rigorously validated over a wide range of geometries and parameters for AlGaN/GaN and AlInN/GaN HEMTs. The model also passes the DC Gummel symmetry test.

Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs

In this paper, we first present a comprehensive study of the unique thermal behavior in monolithic 3-D integrated circuits (ICs) in contrast to through silicon via-based 3-D ICs. In particular, we study the impact of the thin interlayer dielectric between the device tiers on vertical thermal coupling. We then study and compare the impact of different application-based package structures on the thermal behavior of monolithic 3-D ICs. With these unique properties and behavior, we develop a fast and accurate compact full-chip thermal analysis model based on nonlinear regression technique which adapts to the package structure during development and hence considers it during temperature evaluation. Our model is extremely fast and highly accurate with an error of less than 5%. This model is incorporated into a thermal-aware 3-D-floorplanner that runs without significant runtime overhead. We use the floorplanner with our package-aware thermal model and observe up to 22% reduction in the maximum temperature with insignificant area and performance overhead.

A mm-Wave CMOS LC-VCO With Vertically-Coiled Solenoid Inductor

This letter presents a small area mm-wave CMOS LC-VCO with vertically-coiled solenoid inductor. Based on the multi-layers of metals and the vias among them in CMOS process, vertically-coiled solenoid inductor with small area is formed with the inductance at the order of hundred pHs. An accurate compact model for the vertically-coiled solenoid inductor over a broad frequency range has been developed, the method to analytically extract the model parameters is also presented in details. A 24 GHz LC-VCO with the vertically-coiled solenoid inductor was implemented in 90 nm CMOS process. It occupies a core area of 250 $\mu\text{m}$ $\times$ 85 $\mu\text{m}$ , the measured phase noise is $-$ 122 dBc/Hz@10 MHz when the output frequency is 23.6 GHz.

An accurate locally active memristor model for S-type negative differential resistance in NbOx

A number of important commercial applications would benefit from the introduction of easily manufactured devices that exhibit current-controlled, or “S-type,” negative differential resistance (NDR). A leading example is emerging non-volatile memory based on crossbar array architectures. Due to the inherently linear current vs. voltage characteristics of candidate non-volatile memristor memory elements, individual memory cells in these crossbar arrays can be addressed only if a highly non-linear circuit element, termed a “selector,” is incorporated in the cell. Selectors based on a layer of niobium oxide sandwiched between two electrodes have been investigated by a number of groups because the NDR they exhibit provides a promisingly large non-linearity. We have developed a highly accurate compact dynamical model for their electrical conduction that shows that the NDR in these devices results from a thermal feedback mechanism. A series of electrothermal measurements and numerical simulations corroborate this model. These results reveal that the leakage currents can be minimized by thermally isolating the selector or by incorporating materials with larger activation energies for electron motion.

An Accurate Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature.

정확한 기생 성분을 고려한 ITRS roadmap 기반 FinFET 공정 노드별 회로 성능 예측

정확한 기생 성분을 고려한 ITRS roadmap 기반 FinFET 공정 노드별 회로 성능 예측

A novel method of analytically extracting model parameters for stacked transformers

SummaryAn accurate compact model for stacked transformers is proposed. The parasitics between the primary metal coils and the substrate are taken into consideration. The model parameters can be analytically extracted from open‐loaded S‐parameters measured from two‐port test structures. The modeling methodology renders excellent agreement with the data from both simulation and measurement over the frequency range of 0.1–20 GHz for a monolithic stacked transformer manufactured in 0.18‐µm Radio frequency Complementary Metal Oxide Semiconductor (RF CMOS) technology. Copyright © 2015 John Wiley & Sons, Ltd.

An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion

In this paper, we have developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field-effect transistor. The model includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function. The model calculates the drain current using a tangent line approximation method to integrate the tunneling generation rate in the source–body depletion region. The accuracy of the model is tested against 2-D numerical simulations. The model predicts the drain current accurately in both the ON state (strong inversion) as well as in the subthreshold region.

A simulation study of an operational amplifier with non-ideal carbon nanotube transistor: case of scattering effect

This paper presents an extension of the ballistic carbon nanotube field-effect transistor (CNTFET) Raychowdhury [1] compact model with adding acoustic phonon (AP) and optical phonon scattering (OP) mechanisms. These mechanisms cause noise in the device. To obtain an accurate compact model, the flicker and thermal noise-models should be included. This model can be easily implemented with a hardware description language (HDL)-like Verilog-A in the Agilent Advanced Design System simulation tool ADS. The impact of the AP scattering mechanism on operational amplifier (Op Amp) circuit performances is investigated and the simulation results are compared with respect to Op Amp including both AP and OP scattering and to Amp Op using ballistic model. Hence, degradation in the Op Amp performances with AP and OP scattering models is observed especially in gain and bandwidth figure of merits in addition to the increase of the flicker noise in the device.

(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project

DOTSEVEN is a very ambitious European R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project started in October 2012 and will end in March 2016. It is the continuation of the predecessor project DOTFIVE which succeeded to push fmax of SiGe HBTs into the 500 GHz region for the first time. Besides enhancing the speed performance of the SiGe HBT drastically, the challenging task of its integration into a 130 nm BiCMOS process will be addressed too. The capabilities and benefits of the technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development and circuit design will be assisted by improved TCAD and physics-based device simulation and accurate compact device modeling.

(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project

DOTSEVEN is a very ambitious 3.5 year R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project is publically funded within the European Union's Seventh Framework Program for Research (FP7). It started in October 2012 and is now at the beginning of its second year. 10 out of the 12 DOTSEVEN participants were already partnering in the predecessor FP7 project DOTFIVE which succeeded for the first time to push fmax of SiGe HBTs (at room temperature) into the 500 GHz region thus setting a new world-wide benchmark.For a given lithography node, SiGe HBTs provide much higher cut-off frequencies compared to CMOS transistors while offering higher power density and better analog performance. Although ITRS roadmaps [1] predict ever increasing cut-off frequencies for CMOS transistors up to the THz region, there are indications [2,3] that at least fmax will saturate around the 28 nm node at 300-400 GHz (depending on the extraction methodology) and will even drop beyond that node due to parasitic gate resistance [Figure 1]. Thus SiGe HBT technology and SiGe HBT enhanced CMOS (SiGe BiCMOS) will be key enablers for demanding mm-wave systems requiring more than a few µWatts of RF output power (which limits the applicability of even very advanced CMOS) and also offer high integration levels at low cost which precludes expensive and less integrated III-V solutions. Physics based simulations predict “balanced” fT/fmax limits of well above 1 THz for SiGe HBTs [4]. In DOTFIVE the practical performance limits of lateral and vertical scaling of standard HBT topologies which are in use in 200-300 GHz production processes at STM and IFX have shown up clearly. With these conventional DPSA (double poly self aligned) emitter / base structures incorporating an external poly-silicon base-contact which is vertically linked to the SEG (selectively grown) SiGe:C base layer, we were not able to surpass a “400 GHz” limit of fmax significantly [5]. Reaching 500 GHz was only possible with two new transistor architectures realized by IHP employing novel “lateral base-link” [6] or “epitaxial external base-contact” concepts [7] which will be utilized in DOTSEVEN as starting point as they have potential to overcome a basic weakness of conventional DPSA structures: their relatively high-resistive external base-link region [8,9].Within the project the capabilities and benefits of >500 GHz SiGe HBT technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development will be strongly supported by TCAD and physics-based modeling including 3D, nanoscale and thermal effects where as "first-time-right" circuit design will be enabled by accurate compact device modeling including electro-thermal, substrate and other parasitic effects. Of course these models have to be based on accurately extracted parameter sets for which in turn accurate and reliable characterization and extraction methodologies are mandatory. High current densities, excessive self-heating and operation at collector-emitter voltages above the open-base VCE breakdown limit might impose considerable reliability risks in downscaled HBTs and limit their practical application. Therefore in-depth reliability modeling and investigations will be undertaken in the project too.

A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered one of the most promising non-volatile memory candidates thanks to its excellent performance in terms of access speed, endurance, and compatibility to CMOS. However, high power supply voltage is required in the conventional STT-MRAM writing circuit, which results in high power consumption (e.g., ~10 pJ/bit). In addition, it suffers from stochastic switching behavior and process voltage temperature variations. These make power-efficient and reliable write/read circuits become critical challenges. In this paper, we present novel circuits and architectures to build a 16 kb STT-MRAM design with low power and high reliability. For example, the self-enable switching scheme reduces the power consumption effectively and the fore-placed sense amplifier improves the robustness to process variation. Using an accurate compact model of 65 nm STT-MRAM and a commercial CMOS design kit, mixed transient and statistical simulations have been performed to validate this design.

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications. A case study of this nonvolatile flip-flop is considered. In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation. We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ. Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell. At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ.

Maximum-Entropy Density Estimation for MRI Stochastic Surrogate Models

Stochastic spectral methods can generate accurate compact stochastic models for electromagnetic problems with material and geometric uncertainties. This letter presents an improved implementation of the maximum-entropy algorithm to compute the density function of an obtained generalized polynomial chaos expansion in magnetic resonance imaging (MRI) applications. Instead of using statistical moments, we show that the expectations of some orthonormal polynomials can be better constraints for the optimization flow. The proposed algorithm is coupled with a finite element-boundary element method (FEM-BEM) domain decomposition field solver to obtain a robust computational prototyping for MRI problems with low- and high-dimensional uncertainties.