Accelerated Reliability Testing Research Articles

Micro‐via approaches for reducing solder voiding

PurposeThe purpose of this paper is to evaluate the influence of microvia design on solder joint reliability and to present a printed circuit board (PCB) microvia design approach capable of reducing or eliminating voiding in solder joints.Design/methodology/approachFive different types of via‐in‐pad designs were incorporated into a test vehicle and their performance evaluated using a variety of standard reliability tests.FindingsSolid vias, composed of 99.5 percent pure copper can be used to eliminate voiding in solder joints. Such vias are also much more robust than those employing metallic paste or other filled materials. Solid vias with flat surfaces have been shown to be able to meet the requirements of common reliability test standards and to offer a process compatible with traditional PCB manufacturing.Research limitations/implicationsThe occurrence of voiding in solder joints has been shown to be significantly influenced by microvia design. Although a design is reported for reducing/eliminating voiding, other factors that can cause voiding should be investigated. Also, further extended accelerated reliability testing could be undertaken to determine comparative long‐term reliability.Originality/valueSerious voiding in solder joints is a major threat to the quality and reliability of electronics assemblies, mainly due to its role as a stress concentrator and particularly with the move to lead‐free assembly. Methods for reducing and eliminating the occurrence of voiding are needed by electronics assemblers and this work proposes one such method that can be implemented at the circuit board design stage.

Challenges in Qualitative Accelerated Testing of WSN Hardware

Internet of Things (IOT) is a conceptual vision to connect things in order to create a ubiquitous computing world. In order to create such an ever-present network, a simple, reliable, and cost-effective technology is crucial. Wireless sensor network (WSN) is an important wireless technology that has wide variety of applications and provides unlimited future potentials for IOT. Since WSNs in IOT will be used in varying and challenging applications and environments, reliability and reliability testing of WSN hardware becomes extremely important. In accelerated reliability testing, test stresses are increased to cut down the time required to obtain a weakening effect similar to one resulting from normal service conditions in the field. This paper introduces three common difficulties that engineers may experience in qualitative accelerated testing of WSN devices: 1. Challenges in use of standard accelerated tests, 2. Challenges in component-level testing, and 3. Challenges in testing of prototypes. The paper will also introduce examples from real life reliability research and accelerated tests to clarify the presented challenges.

Reliability test and failure analysis of high power LED packages

A new type application specific light emitting diode (LED) package (ASLP) with freeform polycarbonate lens for street lighting is developed, whose manufacturing processes are compatible with a typical LED packaging process. The reliability test methods and failure criterions from different vendors are reviewed and compared. It is found that test methods and failure criterions are quite different. The rapid reliability assessment standards are urgently needed for the LED industry. 85 °C/85 RH with 700 mA is used to test our LED modules with three other vendors for 1000 h, showing no visible degradation in optical performance for our modules, with two other vendors showing significant degradation. Some failure analysis methods such as C-SAM, Nano X-ray CT and optical microscope are used for LED packages. Some failure mechanisms such as delaminations and cracks are detected in the LED packages after the accelerated reliability testing. The finite element simulation method is helpful for the failure analysis and design of the reliability of the LED packaging. One example is used to show one currently used module in industry is vulnerable and may not easily pass the harsh thermal cycle testing.

Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions

Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here. Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism. A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.

The Role of Recrystallization in the Failure of SnAgCu Solder Interconnections Under Thermomechanical Loading

The chip scale packaged/ball grid array component boards were thermally cycled according to the IEC 68-2-14N standard (+125°C/-45°C, 15 min dwells, 5 min ramps). The as-solidified microstructures of Sn-rich solder interconnections were composed of relatively few, typically from two to five, large tin colonies distinguished by high-angle boundaries. However, during the thermal cycling tests the as-solidified microstructures transformed gradually into more or less equiaxed grain structure by recrystallization. It is suggested that cracking of solder interconnections under thermomechanical loadings is enhanced by the recrystallization, because the network of newly formed grain boundaries extending through the interconnections provide favorable paths for cracks to propagate intergranularly. The incubation time of recrystallization was about 50% of the average cycles-to-failure. The decrease of stored energy in high-stacking fault energy metals such as Sn takes place very effective by the recovery. Therefore, microstructures recrystallize only under restricted loading conditions: dynamic loading condition where strain hardening is more effective than recovery. Therefore, the experimentally observable transformation of the microstructures by recrystallization enables us, in principle, to correlate the field use loading conditions with those produced in accelerated reliability tests. Furthermore, the recrystallization provides the means to incorporate the effects of microstructural evolution into the lifetime prediction models.

Research of Accelerated Reliability Test on Server

High-performance computer was developed to address the tight schedule and the high reliability problems. For the 100 trillion times supercomputer Dawning 5000A computing nodes A950r-F server's reliability problems, on the bases of the pre-use investigation and stress analysis of the type, the thesis described the reliability accelerated test of A950r-F server implementation process, and obtained a series of accelerated test data. Accelerated test results from the failure analysis give the corresponding improvement measures by the reliability accelerated test of the A950r-F server. The experiment proved the feasibility and effectiveness of the guidelines.

Accelerated mechanical fatigue testing and lifetime of interconnects in microelectronics

Due to the rapid development of packaging industry accelerated reliability testing for evaluation of lifetime of electronic components are increasingly utilized. In addition to common active thermal cycling procedures, accelerated mechanical fatigue testing provides a new possibility to assess the reliability of microelectronic components, mainly due to the significantly shorter duration of testing time. In this investigation we have used an ultrasonic fatigue testing system in combination with a special experimental set-up for qualification and lifetime determination of microelectronic interconnects. Using this technique, fatigue life of Al wire bonded interconnects were determined and S-N curves (shear stress as a function of loading cycles) up to N=109 were plotted. Three dimensional elasto-plastic FEM simulations were performed to determine the distributions of shear stress and plastic strain generated during cyclic fatigue in the bond area. Furthermore, the FEM model was employed to predict the lifetime of wire-bonds. The results were correlated to the lifetime curves of similar bonds obtained by power cycling tests. Detailed microstructural investigations were performed by means of EBSD -SEM to study the evolution of microstructure of the interconnects subjected to thermal and mechanical fatigue loading. This study demonstrates the applicability of accelerated mechanical fatigue testing as an alternative to time consuming thermal cycling for qualification of microelectronic interconnects.

Accelerated Reliability Test Method(Reliability Data Processing)

Accelerated Reliability Test Method(Reliability Data Processing)

Hot spot analysis during thermal shutdown of SOI BCDMOS half bridge driver for automotive applications

The thermal distribution in large DMOS output transistors of a half-bridge driver IC fabricated in smart-power SOI technology is investigated by the backside transient interferometric mapping (TIM) technique during its thermal shutdown process. The TIM measurements uncovers four hot spots, where the temperature exceeds the limit of the built in temperature sensor. This explains the specific failure mode which was identified during accelerated reliability tests. The TIM results are complemented by temperature measurements with the build-in temperature sensors.

Investigation of environmental reliability of optical polymer waveguides embedded on printed circuit boards

PurposeTo investigate the influences of environmental stresses on board‐embedded polymeric waveguides.Design/methodology/approachOptical multimode waveguides were embedded on printed circuit boards using commercial polymers. The optical‐PCBs varying in board structure and in optical build‐up materials were exposed to heat, moisture and ionic‐contaminants in accelerated reliability tests. The influence of stress factors on the structural integrity and functional parameters, namely the refractive index and optical transmissivity, was investigated at the key communication wavelengths.FindingsIsothermal annealing reduced the refractive index to the greatest extent. The optical‐PCB structure with an optical surface build‐up layer was observed to be more vulnerable under temperature shock when compared with the optical‐PCB with optical inner layer. The buffer layer beneath the optical build‐up was found to improve the stability of the optical waveguides significantly. The results indicated of wavelength dependence to the aging factor with a failure mechanism. The factors affecting the performance and reliability of polymer‐based optical waveguides on PCBs were discussed.Research limitations/implicationsMore experimental data and investigations of failure mechanisms are required to ultimately obtain sufficient reliability statistics for accurate life‐time prediction models.Originality/valueOptical interconnects are seen as a promising solution to overcome performance limitations encountered with high‐frequency electrical interconnections. As an emerging technology, only a limited amount of reliability data on optical/electrical packages is available. The paper investigates the influences of environmental stresses on board‐embedded polymeric waveguides.

Novel Ceramic Composite Substrates for High-Density and High Reliability Packaging

This paper presents the development and evaluation of a large-area carbon-silicon carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (> 200 GPa) and Si-matched coefficient of thermal expansion (CTE) (~ 2.5 ppm/degC) of ceramics. Test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring with microvias on the board. Finite element reliability models were developed to simulate the thermomechanical behavior of test vehicles. From the finite-element simulations as well as accelerated reliability tests, the high stiffness low-CTE C-SiC boards did not show any premature solder joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment and support the multilayer buildup structure required to achieve very high wiring density. The modeling and experimental results suggest that the low-cost large-area ceramic matrix composite (C-SiC) has superior thermomechanical properties, and is, therefore, a promising candidate substrate material for the emerging microelectronic systems.

Improved physical understanding of intermittent failure in continuous monitoring method

Accelerated reliability tests are used to evaluate product life and to ensure a good fit with mission profile. Adequate detecting failure methods and criteria are fundamental to ensure the validity of the test results. In electronic interconnect reliability tests, several types of in-situ electrical continuity methods or manual resistance measurements with crack length analyses are used as failure indicator. Continuous monitoring at high sampling rate shows intermittent signals before permanent failure. In this paper we present a new test approach to improving physical understanding of these intermittent failures. Two different test benches are used to monitor BGA component solder joints under stress. Cross-section analysis, electrical circuit models and signal analysis are used to highlight the relationship between crack propagation and electrical continuity. Finally, basic electric contact theory is applied to explain resistance value fluctuations before permanent failure. The results suggest that high sampling rate in-situ monitoring methods have to be used in order to have an appropriate failure criterion and consequently be more representative of reliability results for electronic interconnects in the field.

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Lead-free Solder Joint Reliability – State of the Art and Perspectives

There is an increasing demand for replacing tin-lead (Sn/Pb) solders with lead-free solders in the electronics industry due to health and environmental concerns. The European Union recently passed a law to ban the use of lead in electronic products. The ban will go into effect in July of 2006. The Japanese electronics industry has worked to eliminate lead from consumer electronic products for several years. Although currently there are no specific regulations banning lead in electronics devices in the United States, many companies and consortiums are working on lead-free solder initiatives including Intel, Motorola, Agilent Technologies, General Electric, Boeing, NEMI and many others to avoid a commercial disadvantage. The solder joints reliability not only depends on the solder joint alloys, but also on the component and PCB metallizations. Reflow profile also has significant impact on lead-free solder joint performance because it influences wetting and microstructure of the solder joint. A majority of researchers use temperature cycling for accelerated reliability testing since the solder joint failure mainly comes from thermal stress due to CTE mismatch. A solder joint failure could be caused by crack initiation and growth or by macroscopic solder facture. There are conflicting views of the reliability comparison between lead-free solders and tin-lead solders. This paper first reviews lead-free solder alloys, lead-free component lead finishes, and lead-free PCB surface finishes. The issue of tin whiskers is also discussed. Next, lead-free solder joint testing methods are presented; finite element modeling of lead-free solder joint reliability is reviewed; and experimental data comparing lead-free and tin-lead solder joint reliability are summarized. Finally the paper gives perspectives of transitions to totally lead-free manufacturing.

Accelerated Testing for Demonstration of Product Lifetime Reliability

This test is designed with the assumption that product reliability is a combination of its individual reliabilities under various operational and environmental stresses and of the undetermined interaction among these stresses. A well-designed reliability test accounts for all cumulative operational and environmental exposures to the stresses that the product will encounter in field use. To determine the level and duration of each of the individual stresses to be applied in the test, it is assumed that the stresses are independent, and a separate factor is added to make up for any unknown stress interactions. The synergism or the test sequence is not disregarded, as it might be the factor contributing to lower demonstrated reliability. The individual stresses are accelerated to allow for reasonable and cost-effective test duration. This test design cannot be accomplished without detailed knowledge of the product's usage profile, sequence of operation, and expected use environments. The choice of test data analysis technique will depend on whether there were any test failures and on the type of failures. Where failures occur, acceleration factors are applied to determine the corresponding times to failure in field use. The test may be conducted as a reliability growth or a fixed duration test by applying the appropriate analytical techniques. The reliability growth technique may be preferred, as it normally yields tests of shorter duration. Accelerated reliability testing provides realistic lifetime reliability demonstration or validation and, if performed early enough, allows for design changes to improve product reliability. In designing any accelerated life test, caution should be exercised to avoid exceeding the environmental rating of the tested product, as high test acceleration can also induce failures that would normally not be expected to occur in the field life of the product. Also, acceleration factors must be carefully determined, preferably through accelerated testing to the failure mode of interest. Acceleration factors (their constants) may be different for different components of the tested products, thus care must be taken in their selection.

Characterization and modeling of static and cyclic relaxation in nonconductive adhesives

Adhesive interconnections are considered to be attractive alternatives to lead or lead-free solder interconnects because of their lower processing temperatures and extendability to fine pitch applications. However, reliability issues, such as moisture-induced delamination and viscoelastic relaxation of the adhesive in both steady-state and cyclic loading, continue to pose a challenge to widespread implementation. To date, the static and cyclic relaxation characteristics of nonconductive adhesives (NCAs) are yet to be understood. This paper attempts to provide insights into this static and cyclic relaxation behavior through experimental characterization and modeling. The viscoelastic property of a typical NCA material was characterized, and a simulation program with integrated circuit emphasis (SPICE) modeling program was used to model the cyclic relaxation behavior. The modeling results were successfully validated with a series of experiments. This showed that cyclic relaxation of the adhesive can be successfully modeled using linear-viscoelastic property. The phenomenon of slower relaxation of the adhesive under cyclic loading than that in static loading suggests that accelerated reliability testing used in solder-joint fatigue durability investigations may not be directly applicable to the adhesive interconnections. A rework methodology applicable to adhesive interconnects using cyclic loading has also been proposed.

Data retention reliability model of NROM nonvolatile memory products

Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.

Reliability enhancement of electronic packages by design of optimal parameters

Reliability growth testing involves the selection of optimal design parameters to enhance a product's reliability. This paper proposes a split plot experimental design that accommodates the restriction on randomization on the order of experimental runs caused by the experimental nature of accelerated reliability testing. The proposed experimental design provides statistically relevant solutions about the choice of design parameters, in terms of their reliability impact, in a much shorter time. A degradation model that aids in predicting the failure time for the given problem further supplements this discussion.

Reliability of MOS devices with tungsten gates

We have investigated the behaviour under accelerated reliability tests of MOS capacitors stressed at high voltage in accumulation with ultra-thin SiO 2 dielectrics and with tungsten gates. Standard p+ poly-Si gates are used as reference. In this report, we show and discuss data concerning the oxide wearout and the breakdown transient.