Accelerated Power Cycling Test Research Articles

Long-Term Lifetime Prediction of Power MOSFET Devices Based on LSTM and GRU Algorithms

Predicting the long-term lifetime of power MOSFET devices plays a central role in the prevention of unprecedented failures for power MOSFETs used in safety-critical applications. The various traditional model-based approaches and statistical and filtering algorithms for prognostics have limitations in terms of handling the dynamic nature of failure precursor degradation data for these devices. In this paper, a prognostic model based on LSTM and GRU is developed that aims at estimating the long-term lifetime of discrete power MOSFETs using dominant failure precursor degradation data. An accelerated power cycling test has been designed and executed to collect failure precursor data. For this purpose, commercially available power MOSFETs passed through power cycling tests at different temperature swing conditions and potential failure precursor data were collected using an automated curve tracer after certain intervals. The on-state resistance degradation data identified as one of the dominant failure precursors and potential aging precursors has been analyzed using RNN, LSTM, and GRU-based algorithms. The LSTM and GRU models have been found to be superior compared to RNN, with MAPE of 0.9%, 0.78%, and 1.72% for MOSFET 1; 0.90%, 0.66%, and 0.6% for MOSFET 5; and 1.05%, 0.9%, and 0.78%, for MOSFET 9, respectively, predicted at 40,000 cycles. In addition, the robustness of these methods is examined using training data at 24,000 and 54,000 cycles of starting points and is able to predict the long-term lifetime accurately, as evaluated by MAPE, MSE, and RMSE metrics. In general, the prediction results showed that the prognostics algorithms developed were trained to provide effective, accurate, and useful lifetime predictions and were found to address the reliability concerns of power MOSFET devices for practical applications.

Real-Time Extraction of SiC mosfets’ Degradation Features Under Improved Accelerated Power Cycling Tests for DC-SSPC Application

The SiC MOSFET is a key component of the DC Solid-State Power Controller (DC-SSPC). The reliability of DC SSPCs can be improved by real-time online monitoring the degradation of SiC MOSFETs. At present, the degradation of SiC MOSFETs can be indirectly monitored using thermo-sensitive electrical parameters(TSEPs), however, their degradation can cause non-negligible measurement errors. Another limitation is that one type TSEPs can only reflect a certain form of degradation processs. Basis on this, in this paper, the real-time extraction method of SiC MOSFETs' degradation features under improved accelerated power cycling tests for DC SSPC application (i.e., average and standard deviation of on-resistance change rate ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avgk</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stdk</i> ) of the improved accelerated power cycling test) is proposed. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avgk</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stdk</i> can be easily obtained by simple calculations. This method can not only directly monitor the severe degradation of bonding wires, but also monitor the severe degradation of the solder layer without measuring the junction temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{J}$</tex-math></inline-formula> ). Compared with the traditional solder layer degradation feature extraction method using thermal resistance which <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{J}$</tex-math></inline-formula> is essential, the monitoring results using the proposed method are not affected by the degradation of TSEPs. Finally, the effectiveness of the proposed method is verified by experiment results.

Investigation of Performance Degradation in 600-V HD-GITs Under Power Cycling Tests

Hybrid drain-embedded gate injection transistors (HD-GITs) are one of the most promising technologies for normally-OFF operation. However, the relevant reliability research is relatively lacking. In this article, comprehensive results of degradation performance in 600-V HD-GITs are presented. First, the thermomechanical stress is applied to the device under test (DUT) through an accelerated power cycling test (PCT) setup. Then, thermal and electrical parameters shift under the PCTs are monitored periodically by the PCT setup and the curve tracer. As can be seen from the measurement results, as the PCT progresses, the device not only exhibits package-level degradation, but chip-level degradation also occurs gradually. Notably, leakage current that increases with degradation appears to be a potential choice for lifetime modeling. Finally, the state-of-the-art failure analysis (FA) techniques, such as emission microscopy (EMMI), scanning electron microscope (SEM), focused ion beam (FIB) cutting, and others, are performed. The results of FAs validated the monitoring data, and the root cause of the degradation of the thermal resistance and electrical parameters was eventually confirmed as the solder degradation and the structural damage of the source and gate. Such an investigation can serve as a valuable reference for the reliability of GaN power devices.

Effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs and its failure analysis

When the SiC MOSFET works in the normal operating conditions, its remaining useful lifetime used to be estimated based on the monitored parameters and the lifetime model derived from accelerated tests. In this case, the degradation caused by abnormal events has not been considered. Therefore, it makes sense to investigate the effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs. A different number of repetitive short-circuit events have been introduced into the accelerated power cycling tests to assess the impact. The experimental results indicate a gate degradation with the increasing number of short-circuit repetitions, which leads to higher conduction loss and earlier failure. Further failure analysis is achieved by performing lock-in thermography, scanning electron microscopy, and focused ion beam.

Analysis of the aging mechanism occurring at the bond-wire contact of IGBT power devices during power cycling

This paper focuses on the degradation at the wire bond contact with the metalized pad, and precisely its evolution with the power module aging. In order to induce damage in this particular zone, an accelerated power cycling test is carried out on well-suited devices. The on-state voltage (VCE) is measured during the test as an indicator of the degradation in the wire and metallization. Then, analyses of the interface wire-metallization are done with a numerical microscope and the EBSD (Electron Back-Scattered Diffraction) technique. As a result, an attempt to correlate the evolution of the degradation with the changes in the granular microstructure of the aluminium constituting the wire and metallization is proposed.

Online Accurate Measurement of Steady-Thermal Resistance of SiC MOSFETs for DC Solid-State Power Controller

The steady-state thermal resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> is the key characteristic of SiC MOSFETs, usually used as a failure indicator. Due to the operating mode of SiC MOSFETs in the dc solid-state power controller (dc-SSPC), the junction temperature measurement based on the steady on-state resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> of SiC MOSFETs is vital to the accurate online measurement of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> . The accuracy of a digital oscilloscope is limited by its analog-to-digital converter; therefore, a drain-source voltage clamp circuit (DVCC) needs to be employed for the accurate online R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement. However, conventional DVCCs are unsuitable for either the use over a wide range of operating temperature T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> or the integration into the dc-SSPC due to their bulk package. Therefore, in this article, a new design of DVCC is proposed that commonly used small-sized components can be easily integrated into the dc-SSPC with a little impact on its overall volume and can accurately perform the online R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement. The experimental results verify the high R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> measurement accuracy (<; 0.6%) of the proposed DVCC over a wide T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> range (25-100 °C), as well as, the accurate online measurement of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> with an accuracy of 2.3%. The application of the proposed DVCC in the accelerated power cycling tests highlights its potential in the lifetime prediction.

Remaining Useful Lifetime estimation for Electronic Power modules using an analytical degradation model

Power electronic modules undergo electro-thermal stresses due to power losses that lead to several kinds of degradations, and finally to failure. In order to prevent power electronic module failure, one should assess its state of health in real-time operation. For this purpose, Prognostics and Health Management (PHM) approach could be a promising tool for reliability evaluation for an IGBT device. The Insulated Gate Bipolar Transistor is a three-terminal power semiconductor device used as an electronic switch which combines high efficiency and fast switching. In this paper, an analytical model is proposed that describes the metallization to wire-bond contact resistance. This model computes the crack length and then using online measurement the rate of crack propagation is computed and used to predict the future crack lengths with the assumption of linearity in crack propagation. The main failure mechanism of the IGBT device in this paper is the crack propagation in the wire-bond interconnection. The usual aging indicator of such damages is the voltage between the collector and the emitter of current (VCE) that increases with degradation. The analytical model is related to this indicator and it is based on the contact resistance theory and constriction current lines. The proposed model is hence used to build a prognostics model for estimating the remaining useful lifetime (RUL) of IGBT power modules. The prognostics model is illustrated using aging data coming from accelerated power cycling tests with different stress conditions. The first cycling test is under the conditions of stress duration ton = 3sec and junction temperature swing amplitudes ΔTj = 110 ºC and the second cycling test is under ton = 3sec and ΔTj = 90ºC. Results show a prognostics capability.

Effects of power cycling test condition and test strategy on lifetime estimation of power modules in power electronic systems

One of the main purposes of an accelerated power cycling test is to develop a lifetime model for the lifetime prediction of power modules. It is important to select proper test conditions when the power cycling test is performed since it is closely related to the lifetime model parameters and also to the testing time. In this paper, the effects of power cycling test condition and test strategy on the lifetime estimation of power modules are studied. The lifetime models of the IGBT module are developed by the accelerated power cycling tests with different test conditions and also by calibrated accelerated power cycling test. As a case study, the lifetime of IGBT module in motor drive system is estimated with different lifetime models and the results are compared.

Comparative study of wire bond degradation under power and mechanical accelerated tests

Degradation of wire bonds under accelerated power cycling tests is compared to that caused by mechanical high-frequency cycling for commercial power devices. Using micro-sectioning approach and optical microscopy it is found that the bond fracture under the mechanical cycling follows the same tendencies as that found under power cycling. Results of shear tests of the mechanically cycled bonds also agree well with the bond cracking tendencies observed by optical microscopy investigations. It is found that reduction of contact area of the wire at the bond/metallization interface due to the crack development follows the Paris-Erdogan law, which defines the degradation rate leading to wire lift-off. The results obtained on mechanical cycling in the current work also show good agreement with literature data on wire bond fracture under power cycling proving that main mechanism for wire lift-off failure is related to the mechanical stress development at the interface with metallization layer. The carried out study also creates a potential to further develop a high-frequency mechanical cycling into an alternative for reliability analysis of wire bonds. However, more studies have to be performed to compare degradation mechanisms occuring under power and mechanical accelerated tests.

Role of Threshold Voltage Shift in Highly Accelerated Power Cycling Tests for SiC MOSFET Modules

In silicon carbide (SiC) power MOSFETs, threshold voltage instability under high-temperature conditions has potential reliability threats to long-term operation. In this paper, the threshold voltage shifts caused by the instability mechanisms in accelerated power cycling tests for SiC MOSFETs are investigated. In conventional power cycling tests, the positive threshold voltage shift can cause successive ON-state resistance increases, which can sequentially increase junction temperature variations gradually under fixed test conditions. In order to distinguish the increased die voltage drop from the bond wire resistance degradation, an independent measurement method is used during the power cycling tests. As the number of cycle increases, SiC die degradation can be observed independently of bond wire increases during the tests. It is studied that the SiC die degradation is associated with the threshold voltage instability mechanisms. Unlike the bond wire lift-off failure, the die degradation and the related die resistance increase can stop the power cycling test earlier than expected. In addition, a new test protocol considering the die degradation is proposed for the power cycling test. By means of power device analyzer, the failure mechanism and the degradation performance of SiC MOSFETs before and after the power cycling test are compared and discussed. Finally, experimental results confirm the role of threshold voltage shifting and identify different failure mechanisms.

Performance Degradation of GaN HEMTs Under Accelerated Power Cycling Tests

Performance Degradation of GaN HEMTs Under Accelerated Power Cycling Tests

Online condition monitoring of IGBT modules using current-change rate identification

Insulated gate bipolar transistors have gained leading position in aerospace and marine applications. However, due to the fact that the power devices are exposed to electrical, thermal and mechanical stresses, the failure rates of these components are comparatively high, and it was found to be the main reason for reducing the reliability of the whole system. Therefore, this paper investigates an IGBT current change rate as a new potential precursor parameter to identify early failure of an IGBT devices. Ageing of IGBT devices and its effect on current change rate is investigated using accelerated power cycling test in order to trigger solder die-attach degradation and bond wire lift-off damage. Experimental investigation verifies that the increase in current change rate is a reflection of die-attach degradation. Lastly, a three-phase inverter system is developed for experiments to verify the proposed method in real time operating conditions.

Failure and Reliability Analysis of a SiC Power Module Based on Stress Comparison to a Si Device

The superior electro-thermal properties of silicon carbide (SiC) power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chips have been adopted for SiC and the different thermomechanical properties cause different fatigue stresses on the solder layer of the chip. In this paper, a 2-D finite element model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs. The proposed model was extrapolated for SiC devices of the same voltage and current rating using the same solder material and the results show that under the same cyclic power loss profile the induced stress and strain energy in the die attach layer is much higher and concentrates on the die/solder interfacial area for SiC chips. Using the validated stress-based model, the lifetime can be quantified when SiC chips are used. This ability to extrapolate the available power cycling and lifetime data of silicon chips to SiC chips would be a key element for developing reliable packaging methods for SiC devices.

Study on Effect of Junction Temperature Swing Duration on Lifetime of Transfer Molded Power IGBT Modules

In this paper, the effect of junction temperature swing duration on lifetime of transfer molded power insulated gate bipolar transistor (IGBT) modules is studied and a relevant lifetime factor is modeled. This study is based on 39 accelerated power cycling test results under six different conditions by an advanced power cycling test setup, which allows tested modules to be operated under more realistic electrical conditions during the power cycling test. The analysis of the test results and the temperature swing duration dependent lifetime factor under different definitions and confidence levels are presented. This study enables to include the t △ Tj effect on lifetime model of IGBT modules for its lifetime estimation and it may result in improved lifetime prediction of IGBT modules under given mission profiles of converters. A postfailure analysis of the tested IGBT modules is also performed.

Failure mechanism analysis of off-state drain-to-source leakage current failure of a commercial 650 V discrete GaN-on-Si HEMT power device by accelerated power cycling test

A gallium nitride on silicon substrate (GaN-on-Si) high-electron-mobility transistor (HEMT) power device is commercially available. The package-level reliability of a GaN-based power device is necessary to respond market demands. Power cycling (PC) tests are a useful method to investigate the reliability of a packaged power component closer to a real application. An off-state drain-to-source leakage current failure (IDSS) of a 650V discrete GaN-on-Si power device under PC test was reported in a previous study. In this paper, to investigate failure mechanism from the last study experiments to verify the root cause are conducted. Scanning acoustic microscope (SAM) images of failure samples exhibit the solder delamination between the discrete chip and the lead frame. The reasonable hypothesis of a correlation between the delamination and IDSS failure is suggested and is tested with a detailed analysis and supplemental experiments. In the process of analyzing the above hypothesis, the new risk of IDSS failure caused by losing electrical connection of silicon substrate rises. The solution for the risk also is proposed. It is discussed that the IDSS failure phenomenon is related to thermal stress induced during PC test. The tests and the analysis indicate that the failure is a thermal stress induced IDSS leakage, not matched previously reported mechanisms.

Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations

Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600V, 30A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.

Advanced Accelerated Power Cycling Test for Reliability Investigation of Power Device Modules

This paper presents an apparatus and methodology for an advanced accelerated power cycling test of insulated-gate bipolar transistor (IGBT) modules. In this test, the accelerated power cycling test can be performed under more realistic electrical operating conditions with online wear-out monitoring of tested power IGBT module. The various realistic electrical operating conditions close to real three-phase converter applications can be achieved by the simple control method. Further, by the proposed concept of applying the temperature stress, it is possible to apply various magnitudes of temperature swing in a short cycle period and to change the temperature cycle period easily. Thanks to a short temperature cycle period, test results can be obtained in a reasonable test time. A detailed explanation of apparatus such as configuration and control methods for the different functions of accelerated power cycling test setup is given. Then, an improved in situ junction temperature estimation method using on-state collector–emitter voltage $V_{{\rm CE}\_{\rm ON}}$ and load current is proposed. In addition, a procedure of advanced accelerated power cycling test and test results with 600 V, 30 A transfer molded IGBT modules are presented in order to verify the validity and effectiveness of the proposed apparatus and methodology. Finally, physics-of-failure analysis of tested IGBT modules is provided.

Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-scale Packages

In this paper, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, was carried out to investigate board-level fatigue reliability of a thin profile and fine pitch ball grid array (TFBGA) chip-scale package under accelerated power cycling test conditions. Experiments for steady-state and transient thermal dissipations were conducted to verify the thermal analysis. Comparing between numerical results for power cycling and thermal cycling, it is noticed that for the tests with similar low and high temperature extremes, power cycling results in a much longer fatigue life than thermal cycling, which indicates that thermal cycling is a more conservative criterion than power cycling is in evaluating the fatigue resistance of the electronic packages.

Failure criteria for long term Accelerated Power Cycling Test linked to electrical turn off SOA on IGBT module. A 4000 hours test on 1200A–3300V module with AlSiC base plate

With AlSiC base plate technology for big module, the reliability about thermal cycling due to railway traction is largely improved and the accelerated Power Cycling Test time is increased a lot to reach over 6 months. Then it appears that these failure indicators as; Rth increasing, Vce increasing, or Iges increasing, must be linked to the interface behavior (thermal and mechanical) and the full electrical capabilities of the device to switch on and switch off current and voltage in a converter.This paper discuss about test methodology and protocol of accelerated Power Cycling Test (PCT), including turn off Safe Operating Area (SOA) measurement before and after reliability tests in order to evaluate the influence of the parameters drift Vce, Rth, and gate leakage Iges.Mainly, PCT and SOA results are presented on 1200A-3300V IGBT module with AlSiC base plate materials after a 4000 hours test (376000 cycles) on very hard conditions. It is also shown the SOA capability on one IGBT module with gate leakage failure.