Accelerated Electromigration Tests Research Articles

Electromigration in Cu–Cu joints: Measurement of activation energy and polarity effect

Electromigration (EM) has been a pivotal reliability challenge for interconnects, but there are only few studies on EM in Cu–Cu joints. In this work, accelerated EM tests for the Cu–Cu joints were conducted at three temperatures (150 °C, 179 °C, and 208 °C) and the temperature-dependent failures were discussed. The polarity effect of the grain growth behaviors at the bonding interfaces was observed at the opposite electron flows, which may be attributed to the difference in EM-build-up stress conditions and the divergence in atomic fluxes. Moreover, the activation energy (Ea) extrapolated from the three EM temperatures was derived as 0.9 eV. As compared to the solder joints with same dimensions, the Cu–Cu joints possess more than ten times of time-to-failures (TTFs) under the same EM condition.

The impact of titanium alloying on altering nanomechanical properties and grain structures of sputter-deposited cobalt for electromigration reliability enhancement

Cobalt (Co) has recently become a highlighted on-chip interconnection material for advanced metallization scheme of microelectronic circuits. Here, electromigration behaviors of sputter-deposited Co and Co(Ti; 0.9 at%) interconnection lines embedded in Si are comparatively studied. These lines were annealed (500 °C/30 min) prior to further accelerated electromigration testing under high current densities in the range of 3 × 107–9 × 108 A cm−2. A collection of the obtained electromigration failure lifetimes, current scaling factors and activation energies confirms a noticeable enhancement in the electromigration reliability of the Co lines by the added Ti. Results by scanning transmission electron microscopy (STEM) and nanoscratch testing reveal that 3–5 nm-sized Ti crystallites are uniformly dispersed in the Co-interconnect matrix, effectively inhibiting Co grain growth, promoting the formation of nanotwinned Co and elevating film’s mechanical properties for ensuring the electromigration reliability. With deteriorated hardness and adhesion energy, reduced planar defects and many big grains all spanning transversely the entire interconnect line, Co is vulnerable to electromigration failures, also giving accelerated thermally-induced interfacial diffusion and chemical reactions with the surrounding Si, as proven by depth-profiling secondary spectrometry and STEM analysis.

Understanding electromigration failure behaviors of narrow cobalt lines and the mechanism of reliability enhancement for extremely dilute alloying of manganese oxide

Self-forming barriers for copper (Cu) interconnect metallization are well developed. However, the self-forming-barrier process and associated electromigration behaviors of narrow lines of cobalt (Co), a new interconnect wiring material for sub-10-nm semiconductor device nodes, are yet to be explored. In this study, we present an all-wet electroless trench-filling process to fabricate narrow (100 nm) lines of Co and MnO-added Co [Co(MnO)], then thermally annealed to some extent (400 °C/30 min) prior to electromigration testing. Empirical data obtained from accelerated electromigration testing, including failure lifetimes, current-density scaling factors, activation energies and physical failure profiles, consistently show that electromigration reliability of the Co lines is markedly enhanced by 0.1% added MnO. Transmission electron microscopy and focused ion beam imaging, along with dynamic adhesion strength data, reveal that the enhancement is related to annealing-induced segregation and dispersion of MnO particles at the interface with SiO2, ensuring adhesion of Co on SiO2, preventing interfacial interdiffusion and stuffing electromigration pathways. The adhesion strength, microstructures and Joule-heating data of Co and Co(MnO) are provided for the discussion of the differences in their electromigration performance and failure mechanism. Comments on electroless-plated Co as a new interconnect material are also given.

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.

Electromigration Activation Energies in Alternative Metal Interconnects

The electromigration (EM) activation energy ( $\text {E}_{\text {A}}$ ) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN $\text {E}_{\text {A}}$ to the EM $\text {E}_{\text {A}}$ in the Ru wires. The calculation of the EM $\text {E}_{\text {A}}$ is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM $\text {E}_{\text {A}}$ then matches the LFN $\text {E}_{\text {A}}$ . For a void at average wire temperature (ambient + JH), $\text {E}_{\text {A}}\approx $ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of $\text {E}_{\text {A}}$ in interconnects.

Modeling Effect of Grain Orientation on Degradation in Tin-Based Solder—Part II: Electromigration Experiments

In a series of articles, we consider the effects of the microstructure and the associated anisotropy of Sn grains on electromigration in lead-free solder bumps. In this article, we carried out experiments to characterize microstructures of tin-based solder bumps and to investigate their effects on electromigration-induced failure. Accelerated electromigration tests and electron backscatter diffraction (EBSD) tests are performed on tin-based solder bumps in wafer-level chip-scale packages (WLCSPs). EBSD analysis, together with the results of time to failure from accelerated electromigration tests, provides valuable information on the effects of the microstructure on electromigration-induced failure that can be used for predictive modeling. For Ni-based metallization, we find that tin self-diffusion is the dominant degradation mechanism and a strong effect of the grain orientation in the solder on the time to failure.

A novel electromigration characterization method based on low-frequency noise measurements

A new electromigration (EM) test method, based on low-frequency noise (LFN) measurements is demonstrated and validated for advanced nano-interconnects, conformable to the 10 nm semiconductor technology nodes and beyond. For the first time, the methodology is applied to electromigration test structures where different metal layers are connected by vias. Firstly, it is established that LFN can be used to calculate electromigration activation energies in via-containing nano-interconnects. This finding is verified by comparing the activation energy obtained by LFN with the one calculated using standard accelerated EM tests on a wide variety of interconnect types. The large correlation between both values (≥90%) indicates that LFN can indeed be applied to successfully determine EM activation energies. Secondly, LFN is shown to provide an indication of electromigration damage in nano-interconnects, which allows linking the noise magnitude with a defect concentration. The first two findings are then combined to provide qualitative predictions of electromigration lifetimes. Two models are proposed: one for void nucleation (the time to form a critical void that will thereafter start growing) and one for void growth (the time between the formation of the critical void and failure, i.e. when the void spans the entire line thickness). Also in this case very strong correlations between LFN measurements and EM experiments were found (≥90% for single metal lines and ≥80% for via-containing structures). The main advantages of using LFN measurements over standard tests for electromigration characterization are that they are non-destructive (no electromigration damage is induced during the test), much faster (a 300 mm wafer can be characterized in a matter of days, as opposed to the weeks it can take using standard EM tests), and that they can be done at test conditions closer to actual operation of the interconnects, such that inducing different mechanisms due to over-stress is avoided.

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> × acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

Estimating the reliability of aluminum metallization of integrated circuits by accelerated electromigration testing at constant temperature

A technique for estimating the reliability of multilayer metallization of integrated circuits at constant temperature has been implemented and tested. Statistical processing of the data has been carried out and the main reliability parameters of conductors have been calculated. The main types of failure, which commonly arise upon electromigration testing at constant temperature, have been demonstrated and analyzed.

Electromigration reliability of open TSV structures

Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analysed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. These results are in good agreement with results of time accelerated electromigration tests.

A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

A 4H-SiC Bipolar Technology for High-temperature Integrated Circuits

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on Aluminium and Platinum. Successful operation of low-voltage bipolar transistor and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27 up to 500 °C for both the metallization systems. When operated on −15 V supply voltage, Aluminium and Platinum OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of Aluminium and Platinum interconnect were evaluated by performing accelerated electromigration tests at 300 °C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors.

Thermomigration of Cu–Sn and Ni–Sn intermetallic compounds during electromigration in Pb-free SnAg solder joints

Abstract

Abnormal Failure Behavior of Sn-3.5Ag Solder Bumps Under Excessive Electric Current Stressing Conditions

Abnormal failure behavior of flip chip Sn-3.5Ag solder bumps with a Cu underbump metallurgy under excessive electric current stressing conditions is investigated with regard to electromigration lifetime characteristics and damage evolution morphologies. Abnormal behavior such as abrupt changes in the slope of the resistance versus stressing time curve correlate well with the changes in mean time to failure and the standard deviation with respect to␣the resistance increase ratio, which seems to be strongly related to highly␣accelerated electromigration test conditions of 120°C to 160°C and 3 × 104 A/cm2 to 4.6 × 104 A/cm2. This is closely related to changes in the damage evolution mechanism with time, even though the activation energy for electrical failure is primarily controlled by Cu diffusion through Cu-Sn intermetallic compound layers.

A Comprehensive TCAD Approach for Assessing Electromigration Reliability of Modern Interconnects

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The demanding task of assessing long-time interconnect reliability can only be achieved by combination of experimental and technology computer-aided design (TCAD) methods. The basis for a TCAD tool is a sophisticated physical model which takes into account the microstructural characteristics of copper. In this paper, a general electromigration model is presented with special focus on the influence of grain boundaries and mechanical stress. The possible calibration and usage scenarios of electromigration tools are discussed. The physical soundness of the model is proved by 3-D simulations of typical dual-damascene structures used in accelerated electromigration testing. </para>

Effects of microstructure on the formation, shape, and motion of voids during electromigration in passivated copper interconnects

In situ scanning electron microscope observations have been performed on passivated damascene Cu interconnect segments of different widths during accelerated electromigration tests. In some cases, voids form and grow at the cathode. However, an alternative failure mode is also observed, during which voids form distant from the cathode end of the interconnect segment and drift toward the cathode, where they eventually lead to failure. The number of observations of this failure mode increased with increasing linewidth. During void motion, the shape and the velocity of the drifting voids varied significantly. Postmortem electron backscattered diffraction (EBSD) analysis was performed after in situ testing, and a correlation of EBSD data with the in situ observations reveals that locations at which voids form, their shape evolution, and their motion all strongly depend on the locations of grain boundaries and the crystallographic orientations of neighboring grains.

Hopf bifurcation, bistability, and onset of current-induced surface wave propagation on void surfaces in metallic thin films

We analyze the electromigration-induced stable wave propagation on surfaces of voids in metallic thin films based on self-consistent numerical simulations of current-driven surface morphological evolution according to a fully nonlinear continuum model. The void surface morphological response is studied for single-crystalline films with twofold and fourfold symmetry of surface diffusional anisotropy, characteristic of <1 1 0>- and <1 0 0>-oriented film planes in face-centered cubic (fcc) metals, respectively, and the effects of the electric-field strength, the surface diffusional anisotropy strength, and the void size are examined. Variation of the above parameters past critical values is found to cause transitions from stable steady to stable oscillatory morphological responses on voids migrating along the films at constant speed; these transitions are the result of Hopf bifurcation at the corresponding critical points. For every bifurcation parameter, the nature of the Hopf bifurcation is determined by the symmetry of the surface diffusional anisotropy on the film plane: the bifurcation is supercritical for fourfold symmetry and subcritical for twofold symmetry. The amplitude and frequency of the void surface oscillations are calculated as a function of the bifurcation parameters and the corresponding bifurcation diagrams are constructed. Our simulations reveal hysteresis phenomena and bistability in both cases of Hopf bifurcation, i.e., for both twofold and fourfold symmetry. For twofold symmetry, i.e., for subcritical Hopf bifurcations, the transitions are between a stable steady state and a stable time-periodic state. For fourfold symmetry, i.e., for supercritical Hopf bifurcations, the transitions may also be between two stable steady states; one of the two steady states bifurcates (upon further variation of the bifurcation parameter) to a time-periodic state at the corresponding Hopf point. The film’s electrical resistance evolution reflecting the void’s morphological evolution is monitored in the regime of oscillatory void morphological response and it is found to be in good agreement with experimental measurements in accelerated electromigration testing.

Three-Dimensional Thermoelectrical Simulation in Flip-Chip Solder Joints with Thick Underbump Metallizations during Accelerated Electromigration Testing

In flip-chip solder joints, thick Cu and Ni films have been used as under bump metallization (UBM) for Pb-free solders. In addition, electromigration has become a crucial reliability concern for fine-pitch flip-chip solder joints. In this paper, the three-dimensional (3-D) finite element method was employed to simulate the current-density and temperature distributions for the eutectic SnPb solder joints with 5-μm Cu, 10-μm Cu, 25-μm Cu, and 25-μm Ni UBMs. It was found that the thicker the UBM is the lower the maximum current density inside the solder. The maximum current density is 4.37 × 104 A/cm2, 1.69 × 104 A/cm2, 7.54 × 103 A/cm2, and 1.34 × 104 A/cm2, respectively, when the solder joints with the above four UBMs are stressed by 0.567 A. The solder joints with thick UBMs can effectively relieve the current crowding effect inside the solder. In addition, the joint with the thicker Cu UBM has a lower Joule heating effect in the solder. The joint with the 25-μm Ni UBM has the highest Joule heating effect among the four models.

Theoretical analysis of current-driven interactions between voids in metallic thin films

We analyze the electromigration-induced interactions between voids in metallic thin films using self-consistent numerical simulations of current-driven void morphological evolution. We focus on the interactions between two voids that, if isolated, they would be morphologically stable and migrate at constant speed along the metallic thin film. It is demonstrated that, under certain electromigration conditions, two such different-sized voids migrating in the same direction along a metallic thin film can lead to stable time-periodic states characterized by wave propagation on a void’s surface or cause failure prior to or following their coalescence. Moreover, various complex phenomena are revealed, including void breakup into two morphologically stable voids following the coalescence of the original two voids and voids attempting to pass each other. In numerous cases, it is noteworthy that the void-void interactions examined arise due to a larger void migrating faster than an originally leading smaller one in a finite-width conducting film with anisotropic material properties, contrary to the conventional notion that smaller voids migrate faster than larger ones for electromigration-driven void motion. These results set the stage toward a fundamental understanding of the current-driven dynamics of populations of interacting voids in metallic interconnect lines. Finally, our analysis predicts that void breakup preceded by void coalescence can cause an abrupt increase in the electrical resistance of an interconnect line, in qualitative agreement with observations from accelerated electromigration testing experiments.

Electromigration issues in lead-free solder joints

As the microelectronic industry advances to Pb-free solders due to environmental concerns, electromigration (EM) has become a critical issue for fine-pitch packaging as the diameter of the solder bump continues decreasing and the current that each bump carries keeps rising owing to higher performance requirement of electronic devices. As stated in 2003 International Technology Roadmap for Semiconductors (ITRS), the EM is expected to be the limiting factor for high-density packages. This paper reviews general background of EM, current understanding of EM in solder joints, and technical hurdles to be addressed as well as possible solutions. It is found that the EM lifetimes of Pb-free solder bumps are between the high-Pb and the eutectic composition under the same testing condition. However, our simulation results show that the electrical and thermal characteristics remain essentially almost the same during accelerated EM tests when the Pb-containing solders are replaced by Pb-free solders, suggesting that the melting points of the solders are likely the dominant factor in determining EM lifetimes. The EM behavior in Pb-free solder is a complicated phenomenon as multiple driving forces coexist in the joints and each joint contains more than four elements with distinct susceptibility to each driving force. Therefore, atomic transport due to electrical and thermal driving forces during EM is also investigated. In addition, several approaches are presented to reduce undesirable current crowding and Joule heating effects to improve EM resistance.