Absolute Detector Research Articles

Optimizing performance: A comprehensive study of 4-bit absolute value detector circuit using static CMOS technology

Optimizing performance: A comprehensive study of 4-bit absolute value detector circuit using static CMOS technology

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

A low-latency and energy-efficient 4-bit absolute value detector for brain-machine interface applications

This research article aims to develop a 4-bit absolute value detector, balancing speed and power efficiency, with potential applications in Brain-Machine Interface (BMI) systems. The detector outputs a binary signal, indicating whether the absolute value of the input surpasses a predefined threshold. The design integrates two primary modules: an absolute value calculator and a comparator. Initially, the study focuses on enhancing the architecture of a multiplexer-based adder for absolute value calculation and selecting an efficient comparator structure, emphasizing least significant bit comparison. Further, the implementation of logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology is elaborated. The research concludes by assessing the minimum delay achievable in the critical path, quantified at 74.22 units, and investigating strategies to minimize energy consumption. This is achieved by adjusting gate dimensions and supply voltage, aiming for a delay 1.5 times the minimum. The energy expenditure of the critical path is extrapolated to estimate the overall circuit consumption. The findings demonstrate that, at 1.5 times the minimal delay, the circuit achieves a maximum energy savings of 62.8% with a supply voltage of 0.815V.

Optimized design of a 4-bits absolute-value detector based on linear programming

Nowadays, neural signal acquisition systems are constantly developing, and spike classification algorithms have been widely studied and concerned. This paper designed a practical spike detection circuit, named as the absolute value detector. Project is committed to adopting only simple gate circuits, by using Morgans theorem to optimize the circuit structure, so that we can ensure that the detector has the following several advantages, simple and beautiful, easy to understand, powerful performance. In addition, this paper also considered the optimization of performance including latency and energy consumption. The increase of Vdd will increase the energy consumption and reduce the delay, while the increase of size will reduce the energy consumption and increase the delay. Using MATLAB software for linear programming, Under the condition of a 1.5-fold increase in the delay, and then adjusting Vdd and size, energy consumption was down by 78 percent.

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.

Optimization of 4-bit absolute value detector based on CMOS and PTL

This article designed and optimized a 4-bit absolute-value detector mostly using Complementary Metal Oxide Semiconductor (CMOS) static logic and transmission gate logic (PTL). In terms of overall architecture, the implementation of logic circuit functions is primarily separated into two modules, including the absolute value detector and the comparator. This paper identified the critical path of the final detector and conducted research and simplification on it to improve the general functionality of the detector which can compare the value of two numbers. To shorten the delay time in the circuit, this paper reduced the number of components on the crucial path. After calculating, the critical path delay is approximately 61.065 and the initial energy consumption for a minimum path delay is 51.06. To obtain the least amount of delay and energy use, three different techniques were used in this investigation. Ultimately, we found that the circuit optimized using the Changing V_DD and Sizing method was the most efficient. The optimized critical path delay remained around 61.065, and the energy consumption under optimized critical path delay was reduced to 10.845. The final implementation achieved a decrease of 82.2% in energy consumption while maintaining the critical path delay unchanged.

A 6-bit absolute value detector based on MOSFET and PTL structure

As science and technology develop fast, people nowadays can have an easy approach to various advanced products. The use of Internet of Things has become a reality. To ensure its reliable implementation in daily life, stable and efficient hardware equipment like sensor is essential, where absolute value detector is widely used. A detector is created on the basis of this. The circuit can compare a signed 6-bit number with the threshold of a 5-bit number. This design uses MOS and pass-transistor logic (PLT) structure as the basic parts to form the transcoding logic and the subtraction logic. This paper also discusses the optimization of its minimum latency and energy usage based on logic effort parameters. In order to match a sequence of minimum delays, the article gives various power supply voltages and calculates each schemes lowest energy consumption for each voltage. The reduction of the energy cost is significant, which means the circuit has application value in reality. Besides, the different results are listed in a scatterplot to find out the trend of optimization, which may be helpful for selecting a proper scheme in the real program.

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

A New Design of A 6-Bit Absolute Value Detector by Using Both VDD Scaling and Sizing to Optimize

The presented paper focuses on the development and optimization of a 6-bit absolute value detector, a crucial digital block in encoder and decoder applications. The primary objective is to minimize energy consumption while maintaining a delay no greater than 1.5 times the minimum delay. The optimization process combines logical effort theory with gate sizing and voltage scaling techniques. Firstly, gate sizes are adjusted while keeping VDD constant, achieving a 73% reduction in energy consumption, reaching a delay constraint of 1.5 times the minimum delay. Secondly, VDD scaling is explored without altering gate sizes, resulting in a 40% reduction in energy consumption, reaching the minimum energy consumption point. Finally, gate sizing and VDD scaling are combined, yielding a remarkable 79% reduction in total energy consumption, with a supply voltage of 0.835 volts. These optimization strategies bridge a research gap in 6-bit absolute value detectors, significantly enhancing energy efficiency and offering valuable insights for intricate digital signal processing scenarios. The findings showcase the effectiveness of combining logical effort theory with gate sizing and voltage scaling to achieve substantial energy savings while meeting stringent delay constraints.

An Optimized Design Of 8-Bit Absolute Value Detector Based on CMOS And Logic Effort Theory

Absolute value detecting is widely involved in integrated digital circuits. Currently absolute value comparison happens frequently in digital integrated circuits such as RISC structure micro controllers. Considering the requirements of corresponding products, an 8-bit absolute value detector is designed and optimized in this essay. Compared with some similar magnitude comparators existing on the market, this scheme supports 2’s complement input to realize calculation and comparison of absolute values. The basic structure of the design is a Complementary Metal Oxide Semiconductor (CMOS) logic gate circuit which is redesigned in order to reduce the number of transistors involved. The circuit was then further optimized in size and source voltage based on logic effort theory. Based on that, the size of logic gates and V_DD are properly adjusted to optimize both speed and energy efficiency. The final version realized a 20.12% energy consumption when the delay is 1.5 times of minimum value. In the future, similar method could be applied for optimization of other digital circuits in order to improve the performance of corresponding produces.

Circuit design and energy optimization strategy for a four-bit absolute value detector

The demands placed on the quality of products and services within the realm of electronic technology have reached unprecedented heights. The utilization of electronic decoders has thus become incredibly extensive to meet these evolving needs. Among the integral components of electronic decoders, the absolute value detector holds a significant position. In our pursuit to enhance the efficiency of electronic decoders, this paper have identified substantial room for improvement within the currently prevalent absolute value detector designs. This paper introduces a novel absolute value detector design scheme that promises remarkable advancements. It is worth noting that the performance of this newly proposed absolute value detector far surpasses that of the traditional counterparts. Through rigorous calculations and testing, our absolute value detector exhibits an impressive performance profile, boasting a delay of 34.13FO4 (1V) and an energy consumption of 184.832Eu (1V). These results undoubtedly hold the potential to catalyze innovation in digital decoder technology, offering fresh insights into how we can elevate the overall quality of digital decoders. This contribution paves the way for product enhancements and serves as a valuable resource for those striving to stay at the forefront of electronic technology advancements in our fast-paced information-driven society.

Trade-offs Between Delay and Energy in 4-Bit Absolute Value Detector and its application analysis

With the rapid advancements in digital signal processing and communication technology, the utilization of digital detectors has become prevalent across numerous domains. Among these detectors, absolute value detectors hold particular significance. This article primarily delves into the delicate balance between latency and energy consumption within the realm of 4-bit absolute value detectors. To commence, we provide an exhaustive exposition of the fundamental design and operational principles underpinning absolute value detectors. Subsequently, we embark on a comprehensive comparison of various optimization approaches, with a special focus on their efficacy concerning energy consumption and latency. The research endeavors have unveiled that the detector's optimal aspect ratio, as well as the choice of novel materials like graphene and silicon germanium, can wield a substantial influence over its performance. As its peer into the horizon, it is evident that the continuous evolution of new materials and cutting-edge technologies promises further enhancements in the performance of 4-bit absolute value detectors.

Design and Optimization of a CMOS-based 4-bit Absolute Value Detector

This research paper introduces a meticulously crafted blueprint for a 4-bit Absolute Value Detector (AVD) utilizing cutting-edge Complementary Metal-Oxide-Semiconductor (CMOS) technology. The proposed architectural marvel has been specifically fine-tuned to cater to the demands of high-speed, energy-efficient applications, making it applicable across a wide spectrum of signal-processing domains. At its core, this design harnesses the synergistic power of multiplexers, a ripple carry adder, and a comparator, strategically orchestrated to swiftly and accurately determine the absolute magnitude of the input signal, subsequently comparing it against a predefined threshold. The resultant circuit stands as a testament to its prowess, boasting a remarkably low latency while maintaining commendably low power consumption and a robust resistance to external noise interference. In doing so, it not only aligns itself with the contemporary requirements of rapid real-time signal processing but also paves the way for scalability, positioning itself as a viable solution for more intricate and demanding applications. By doing so, this innovation not only contributes to the ongoing evolution of electronic technologies but also sets the stage for future research endeavors, promising a brighter and more sophisticated future for the field.

Encrypt ECG signals based on the optimized 4-bit absolute value comparator

As people become more conscious of private information security and advancements in Electrocardiogram (ECG) identity identification technology, the need to encrypt private data intensifies. New wearable medical devices continuously gather vast amounts of personal health data, underscoring the urgency of safeguarding privacy. This paper focuses on encrypting and decrypting rich characteristic signals like ECG. It delves into the core aspects, including the logic circuit diagram of a four-bit digit absolute comparator using Complementary Metal Oxide Semiconductor (CMOS) technology and optimizing delay through logic effort to reduce power consumption. XOR gates and other gate circuits, as well as complement subtraction principles, are employed in building logic gates. Calculating delay involves selecting the longest critical path and determining the specific parameters (g, h, and p) for each logic gate. Subsequently, energy consumption is computed using a formula, revealing a trade-off between energy and delay. After optimization, the circuit's energy consumption is 184.832, and the delay is 34.13. In summary, the 4-bit absolute value detector plays a crucial role in encryption, addressing the growing concern for privacy and data security.

Design of 4-bit absolute value detector with low energy

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

The accuracy analysis of different algorithms for 4-Bit absolute value detector

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.

Design and implementation of 4-bit absolute value detector based on verilog HDL

Absolute value detectors are widely utilized in many disciplines, such as image processing, speech recognition, and control systems, due to the advancement of digital signal processing and computer vision technologies. This paper presents a 4-bit absolute value detector based on the Verilog HDL programming language. Absolute value detectors are extensively used in signal processing, computer vision, and other fields to determine if the absolute value of the input signal meets specific conditions. This paper describes in detail the design process, including module analysis, the drawing of state transfer diagrams, the writing of Verilog HDL code, and simulation verification with a focus on practical applications. The results demonstrate that the absolute value detector is accurate and reliable in determining whether the absolute value of the input signal is greater than or equal to the threshold value.

4-bit absolute value detection for digital signal processing applications

In recent years, as the rapid advancement of the electronic industry and the higher requirements for instruments and circuits, the absolute value circuit has found an increasingly wide utilization in digital signal processing. An absolute value detector is one of the most widely used algorithms used for detecting spikes. Based on traditional designs of absolute value circuits, many optimized designs with better performance have been proposed. Based on previous analysis and research, absolute value circuits can be optimized into different sructures to meet different application requirements. This paper introduces three different absolute value circuits for different uses in digital signal processing by comparing the optimized parts to traditional absolute value circuits and introducing how the optimization can meet the needs of different applications. These optimized absolute value circuit meet the requirements of higher precision and more stable temperature in biological signal processing field, more convenient to apply in the analog-to-digital conversion in ADC field and minimization the latency energy in chip signal processing field. Absolute value circuits can be optimized in different ways to be applied in more fields in the future.

Towards the use of SDD as an absolute detector for high-energy neutron measurements

As of today, the standard method employed in tokamaks for the absolute measurement of the neutron flux (thus of the nuclear fusion power) is based on activation foils, being the most robust and unbiased technique for the absolute determination of neutron fluence. However, this technique is not able to provide real-time data useful for the control of future fusion plants like DEMO. In this paper, we present some preliminary results about the R&D activity aimed at developing the Single-crystal Diamond Detectors (SDD) used for fast neutron measurements into an absolute neutron flux monitor. Tests have been conducted at the new NILE neutron source of the Rutherford-Appleton Laboratory, a facility with compact neutron generators with a maximum yield of 109 n/s and 1010 n/s for 2.5 MeV and 14 MeV neutrons, respectively. A series of neutron spectra and flux measurements have been taken with different SDD and associated DAQ. Comparisons with standard activation foils (and namely Fe, Zr, Al and Nb foils for 14 MeV neutrons and In for 2.5 MeV neutrons) and with other reference detectors are presented and discussed. Also discussed is the stability of the SDD over time when employed at high neutron rates in realistic neutron environment, and the effects of neutron irradiation on both the counting rate and detector resolution.

Optimized Design of a 4-bits Absolute-Value Detector

4-bits Absolute Value Detector circuit is a very commonly used circuit design. As to simplify the internal circuit design to make the total number of stage lesser which provides a less critical path circuit delay. Generally, this paper used combination of static CMOS design and the path transistor circuit design to design our circuit. After we got the optimized design, we applied the logic effort calculation to calculate the minimum delay of the circuit and determined the specific gate sizing value for each logic component. The energy optimization can be obtained by increasing our delay and adjusting the power supply (VDD) value. Eventually, we sacrifice our delay a little bit to get a huge amount of energy reduction.