An Optimized Design Of 8-Bit Absolute Value Detector Based on CMOS And Logic Effort Theory

Abstract

Absolute value detecting is widely involved in integrated digital circuits. Currently absolute value comparison happens frequently in digital integrated circuits such as RISC structure micro controllers. Considering the requirements of corresponding products, an 8-bit absolute value detector is designed and optimized in this essay. Compared with some similar magnitude comparators existing on the market, this scheme supports 2’s complement input to realize calculation and comparison of absolute values. The basic structure of the design is a Complementary Metal Oxide Semiconductor (CMOS) logic gate circuit which is redesigned in order to reduce the number of transistors involved. The circuit was then further optimized in size and source voltage based on logic effort theory. Based on that, the size of logic gates and V_DD are properly adjusted to optimize both speed and energy efficiency. The final version realized a 20.12% energy consumption when the delay is 1.5 times of minimum value. In the future, similar method could be applied for optimization of other digital circuits in order to improve the performance of corresponding produces.