6T SRAM Research Articles

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM).

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Cryptography is crucial in embedded systems for safeguarding sensitive information, maintaining data integrity, and facilitating secure communication. L1 cache memory enhances overall performance by temporarily storing cryptographic keys. Post-quantum cryptography (PQC) focuses on creating algorithms that stay secure even against quantum computing threats. However, PQC doesn't fully protect against side-channel attacks (SCA). As IoT devices like wearable health monitors and industrial sensors become more widespread, the demand for lightweight cryptography increases to balance security with resource constraints. Yet, lightweight cryptography can face challenges, including reduced security and increased susceptibility to SCA due to smaller key sizes. Attackers can exploit power consumption patterns through side-channel attacks (SCA), such as Power Analysis, to extract these secret keys. Once a key is compromised, encrypted data becomes vulnerable. In cloud computing cache side-channel attacks take advantage of multiple virtual machines running simultaneously on the same hardware, enabling them to extract sensitive information from encryption processes. Although many SRAM cells have been designed in the literature, none offer complete security against SCA. This paper presents a new architecture for secure cache memory using a proposed 10T SRAM cell that secures all three cell operations (read, write, and hold) against SCA attacks. Additionally, this architecture also prevents half selection issue in cache memory. The security measure of proposed-10T cell is 97.19 % which is highest among all other cells and reliability measure is 82.03 %.The cell also offers highest hold stability of 421 mV along with good read stability and write ability of 220 mV and 334 mV respectively. The leakage of Proposed-10T cell is also less i.e., 13.56 pA. The Performance and Security Factor (PSF) is computed for all considered cells, encompassing various performance and security metrics. The normalized PSF (PSF)N of the Proposed-10T cell is 2.17, the highest among all cells considered for comparison. Therefore, the Proposed-10T cell architecture is fully secure against SCA and achieves better performance during cell operations.

Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node

Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations. Tools used: LTSpice v17 is the tool used to design the schematic circuits and to obtain the simulation results. The library file used to design the schematic is the 16nm technology node from the library of the Arizona State University’s Predictive Technology Model (ASU-PTM). Methods: To perform a comparative study of the 8T SRAM and 20T TICE, the schematic circuits were designed using the 16nm technology node in LTSpice. A baseline for the expected voltages of logic 0 and logic 1 is established before injecting errors at the sensitive voltage nodes of the circuit. The next step is to manually inject bit upsets at the crucial nodes of the memory cell to induce either a 0-1 upset or a 1-0 upset. The read/write operation is carried out along with the error injection to compare the error mitigation capacity of the circuits. Finally, the results are tabulated to prove that the 20T TICE is resilient to soft errors arising from exposure to high radiation. Results: During the normal operation of the 8T SRAM cell, the observed output voltage corresponding to logic 0 and logic 1 are 25mV and 780mV respectively. The voltage levels increased to 400mV during a 0-1 upset and dropped to 25mV during a 0-1 bit upset. This indicates that the cell is not reliable. In case of the 20T RHBD cell, the voltage levels for the normal operation were 5mV (logic 0) and 780mV (logic 1). The major improvement is shown in the case where the 20T TICE is injected with bit upsets, since it delivers a voltage of just 6mV during a 0-1 bit upset and maintains a voltage of 770mV during a 1-0 bit upset. Conclusion: The work performs the schematic designs for the comparison of the error mitigation capabilities of a 8T SRAM cell and a 20T TICE which is radiation hardened by design. The study proves that the 20T cell is capable of successfully mitigating both a 1-0 bit upset and a 0-1 bit upset

Solution to SRAM static power consumption with MTCMOS

The rapid growth of mobile devices has led to an increasing demand for battery life and energy efficiency in recent years, the reduction of circuit power consumption has become extremely crucial. SRAM has become an indispensable component of modern System-on-Chip (SoC) designs, and reducing its power consumption holds significant importance in minimizing overall chip power consumption. On the other hand, as manufacturing processes advance, static power consumption resulting from leakage currents has gradually emerged as a primary source of power consumption. This paper analyzes the power composition of SRAM, provides a detailed explanation of the principles and influencing factors of MTCMOS design technology, and conducts modeling analysis on 6T SRAM based on MTCMOS. In the modeling analysis, we compare the leakage current and static power reduction effects of 6T SRAM using four different process technologies: 28nm, 40nm, 65nm, and 90nm. From the data, it can be observed that MTCMOS has a notable effect in reducing leakage current for 6T SRAM across various process technologies. Comparing 6T SRAM of different process technologies, we can roughly see that the power reduction effect reaches a peak and gradually decreases. However, due to the lack of more advanced process libraries, we cannot further validate whether this inference is accurate.

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices

Compute-in-memory has been increasingly appreciated by researchers as a well-suited hardware accelerator in convolutional neural networks (CNNs), because it can achieve low power consumption and high inference accuracy. This work presents a novel TD-CIM structure using:1) A Capacitor Charging scheme that uses Compact 8T Model for multiply-and-accumulate (MAC) Operations with serials inputs in Time Domain Level; 2) a new replicated bit-line time-domain converter (RBL-TDC) to achieve the quantization of the multiply-accumulate operations with high accuracy; 3) A 22 nm FD-SOI 16 Kb TD-CIM macro fabricated using foundry provided compact 8T-SRAM cells, which achieves normalized energy efficiency(EF) of 5816.5 TOPS/W, normalized area efficiency(64TOPS/mm2), and 8-bit weight for 8-bit serials inputs with 64 accumulations per cycle, as well as output precision(14b) in the MAC operation. This work also obtains an inference accuracy of 92.57 % on the VGG-16 network using the Cifar10 dataset over PVT variations.

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28 nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology

The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for creating schematic diagrams and layouts, while the ASSURA library is employed for conducting design rule checks (DRC) and layout versus schematic (LVS) comparisons to verify the alignment between the layout and the schematic. In the process, a low VDD of 1 V is taken for the design. The results shows that 10T SRAM is efficient in terms of read and write delay and power consumptions.

Design and Implementation of High Speed SRAM Cell

Static Random Access Memory's main design goals are to have a consuming low power and high speed, as technology is developing at a faster paceand this has given rise to new challenges.The high speed along with stability of SRAM are important issues to improve efficiency and performance of the system. This proposed work presents design and implementation of 1Kb 6T SRAM using CMOS technologies by using EDA tool. In this proposed work, SRAM’s cell is operated in 1V voltage. Our proposed high speed SRAM consisting 6T achieved read delay and write delay of 29.4ps & 15ps respectively. And also our designed cell has stability of 70 mV & 195 mV for read SNM and write SNM respectively

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset

This research paper introduces a memory architecture that handles standard memory storage operations and enables in-memory computations, surpassing the capabilities of conventional SRAM bit-cells. The proposed architecture in this work effectively eliminates read-disturb issues and facilitates bit-wise operations like NAND, NOR, and XNOR, all without requiring intricate analog peripheral circuits. The suggested bit-cell architecture offers enhanced throughput compared to existing In-Memory Computing (IMC) bit-cell architectures, making it a more suitable design for IMC applications. Parallelism offers enhanced throughput due to the unique bit-cell architecture, which allows all the bit-wise operations to be achieved simultaneously in a single cycle. The validity of the suggested architecture has been confirmed through Monte-Carlo variation analysis, utilizing UMC 28 nm PDK transistor models to ensure its robustness. Furthermore, architecture is benchmarked using the CIFAR-10 dataset, which entails assessing its performance across various machine learning models via the NeuroSim Simulator. The proposed architecture offers a substantial increase of up to 40 % in throughput (TOPS/W) compared to the existing architectures. Utilizing accurate Monte-Carlo simulations with 1000 samples, the stability of the proposed 10T bit-cell is validated at worst-case PVT corners, up to 6σ variations.

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

Evaluation of a Simplified Modeling Approach for SEE Cross-Section Prediction: A Case Study of SEU on 6T SRAM Cells

Electrical models play a crucial role in assessing the radiation sensitivity of devices. However, since they are usually not provided for end users, it is essential to have alternative modeling approaches to optimize circuit design before irradiation tests, and to support the understanding of post-irradiation data. This work proposes a novel simplified methodology to evaluate the single-event effects (SEEs) cross-section. To validate the proposed approach, we consider the 6T SRAM cell a case study in four technological nodes. The modeling considers layout features and the doping profile, presenting ways to estimate unknown parameters. The accuracy and limitations are determined by comparing our simulations with actual experimental data. The results demonstrated a strong correlation with irradiation data, without requiring any fitting of the simulation results or access to process design kit (PDK) data. This proves that our approach is a reliable method for calculating the single-event upset (SEU) cross-section for heavy-ion irradiation.

A novel single-ended 9T SRAM cell with write assist and decoupled read path for efficient low-voltage applications

A novel single-ended 9T SRAM cell with write assist and decoupled read path for efficient low-voltage applications

A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection

A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

As the technology has rapidly evolved and also high-speed task implementation has come into picture the chance for an error to occur has also increased though there are many precision algorithms to increase the precision of the system significantly this paper proposes one such error reducing application for aerospace applications. Using a Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications (QUCCE12T) is more susceptible to data loss as the QUCCE12T SRAM has high sensitivity and the sensitive nodes are at higher risk. To reduce this, we propose to use Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM (SREWH12T). Basically, the initial thought is to reduce the soft error created by voltage drops by passing the data through the inverters. The Single Event Upset (SEU) that arise in the usage of QUCCE12T SRAM can be recovered using a SREWH12T SRAM instead. The sensitive components of SREWH12T have the capability to recover their data even in cases where the values have been altered by radiation impact. The SREWH12T SRAM cell to mitigate upsets, compares it with other cells, and demonstrates its superior performance in terms of soft-error tolerance, recovery from upsets and having low power consumption. Furthermore, the added advantage of SREWH12T cell is that it can recover from Single Event Multiple Nodes Upset (SEMNU). Average power consumed by SREWH12T is 2.988363e-007 watts. Along with this the SREWH12T SRAM can provide high write stability due to its recovery rate. All these added advantages and recovery of data all comes at high utility range and with slightly high read energy consumption, which is very minimal, the system also exhibits slightly high read delay.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.