16-bit Multiplier Research Articles

Realization of 2-bit multiplier based on Vedic mathematics using electro-absorption microring modulator

Realization of 2-bit multiplier based on Vedic mathematics using electro-absorption microring modulator

Adaptive prairie dog optimization based variable length conditional counter for designing multiplier

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

Image Multiplication Using Novel 4:1 Approximate Compressor

Energy-efficient designs are the need of the hour for signal and image processing applications that are error-tolerant. The paper proposes a new 4:1 approximate arithmetic-based compressor developed by analyzing the probability-based tactics that have a higher degree of precision when implemented. Approximate n × n multiplier is designed using the proposed varying probability-based compressors. To validate the effectiveness of the new compressor, a 16 × 16 multiplier is designed. The n × n bit multiplier will have 2 n columns of partial products(PP), in which the least significant n−1 columns are designed using the novel approximate 4:1 compressor and most n + 1 columns are designed with the exact compressor. The results of the 16-bit multiplier are superior to the performance of the exact multiplier in terms of power, area, power-delay-product (PDP), and area-delay-product (ADP) typically by 39 % , 20 % , 44 % , and 26 % respectively for Design 1 and 14 % , 24 % , 30 % , and 21 % , respectively for Design 2. The Peak Signal to Noise Ratio(PSNR), Mean Square Error(MSE), and Structural Similarity Index Measure(SSIM) for the output images processed by new approximate multipliers are acceptable when compared with precision and energy.

Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 μm2, delay is 3.01 ns, power consumption is 0.021 mW and power delay product is 119 fJ.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing

This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancing area and energy efficiency. Consequently, there are 84% fewer choices of input-output combinations, thereby decreasing the circuit complexity with respect to area and energy usage. When compared to its existing counterparts, the suggested 5:3 compressor improves area utilization and energy usage by an average of 11%, 17%, and 17% in 8-, 16-, and 32-bit multipliers, respectively. The results of simulations demonstrate the superiority of our method over traditional designs, providing an increase in both area and energy efficiency. These results highlight the applicability and scalability of our method, which is appropriate for a variety of applications such as embedded systems and digital signal processing.

AxOMaP : Designing FPGA-based A ppro x imate Arithmetic O perators using Ma thematical P rogramming

With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resource-constrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI/ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-specific AxOs.

Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done. Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics

An efficient approximate multiplier: Design, error analysis and application

Approximate circuits are extensively considered in error-resilient applications to reduce the design complexity. A multiplier is known as a key arithmetic unit of computational block, and thus improving the performance of the multiplier is significantly important to achieve an effective processor. In this paper, we develop two new inaccurate multipliers using approximate 4:2 compressor. Applying error correction block in the structure of these 8-bit multipliers remarkably increases the accuracy of design. The design performance and error metrics of the multipliers are analyzed. Furthermore, as an image processing application, we consider several benchmark images, and compare the quality metrics of image multiplication of our proposed multipliers to those obtained from different under-test multipliers of the previous studies. The design of multipliers is performed using HSPICE with 14 nm FinFET technology. The results demonstrate that the proposed multipliers provide suitable efficiency in the error analysis when compared to the exact multiplier in image processing application.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

Agile-Quant: Activation-Guided Quantization for Faster Inference of LLMs on the Edge

Large Language Models (LLMs) stand out for their impressive performance in intricate language modeling tasks. However, their demanding computational and memory needs pose obstacles for broad use on edge devices. Quantization is then introduced to boost LLMs' on-device efficiency. Recent works show that 8-bit or lower weight quantization is feasible with minimal impact on end-to-end task performance, while the activation is still not quantized. On the other hand, mainstream commodity edge devices still struggle to execute these sub-8-bit quantized networks effectively. In this paper, we propose Agile-Quant, an Activation-Guided quantization framework for faster Inference of popular Large Language Models (LLMs) on the Edge. Considering the hardware profiling and activation analysis, we first introduce a basic activation quantization strategy to balance the trade-off of task performance and real inference speed. Then we leverage the activation-aware token pruning technique to reduce the outliers and the adverse impact on attentivity. Ultimately, we utilize the SIMD-based 4-bit multiplier and our efficient TRIP matrix multiplication to implement the accelerator for LLMs on the edge. We apply our framework on different scales of LLMs including LLaMA, OPT, and BLOOM with 4-bit or 8-bit for the activation and 4-bit for the weight quantization. Experiments show that Agile-Quant achieves simultaneous quantization of model weights and activations while maintaining task performance comparable to existing weight-only quantization methods. Moreover, in the 8- and 4-bit scenario, Agile-Quant achieves an on-device speedup of up to 2.55x compared to its FP16 counterparts across multiple edge devices, marking a pioneering advancement in this domain.

Modeling the effects of power efficient approximate multipliers in radio astronomy correlators

Large scale Radio Telescopes for Radio Astronomy highly depend on the availability of large (digital) processing capacities for imaging. Estimates concerning power efficiency for future Radio Telescopes lead to anticipated power consumption numbers beyond feasibility. To reduce the power budget, the use of approximate multipliers within the correlator is explored. A baseband equivalent executable model of a radio synthesis telescope is constructed to assess the effects of approximate multipliers. Besides ideal multipliers with floating point accuracy, the use of accurate 8-bit multipliers and 4 different types of approximate multipliers is explored. For each of these multipliers, the energy efficiency of an individual multiplier is known and used to determine the energy efficiency improvement of a correlator when using approximate multipliers. The effects of approximation are quantified by 3 metrics (Signal-to-Noise-Ratio (SNR), Spurious-Free-Dynamic-Range (SFDR) and Root-Mean-Square (RMS) level) derived from maps constructed by the executable model based on an empty sky with only a single point source. This is considered to be the worst case scenario. For illustration purposes, a more realistic input is processed by the model as well. The metrics have been determined based on different SNR levels at the input of each antenna element. For input SNR levels up to 10 dB, all types of approximate multipliers used in this paper can be exploited to improve energy efficiency of correlators, leading to a maximum energy reduction of 19 %. For input SNR values up to 30 dB an energy improvement up to 12 % can be achieved. These percentages are based on implementations in a 40nm low power IC technology at 1 GHz.

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

With the expanding computer application scenarios and increasing computational demands, optimizing 16-bit multiplication is an important and meaningful research topic. In this paper, we take advantage of the parallel computing property of Wallace tree and the advantage of bit-level operation of Booth algorithm to perform certain optimization on 16-bit multiplier. In this paper, a series of basic modules are firstly constructed as the basic framework of the multiplier, and then the optimization module is designed by using Booth algorithm and Wallace tree, and they are combined to obtain a multiplier with improved computational accuracy, reduced computational complexity, reduced delay, and improved computational efficiency compared with the traditional multiplier. The significance of the optimized multiplier implementation is to increase the computational speed, improve the chip resource utilization, reduce the power consumption and energy consumption, and meet the demand of complex applications, which is of great significance to improve the performance and efficiency of computer systems.

Optical 2-bit nanoscale multiplier using MIM waveguides.

The plasmonic 2-bit multiplier is designed at a 1310nm operating wavelength and a 65% transmission threshold (T t h r e s h o l d ). Using the finite element method (FEM) with the COMSOL version 15 software, we simulated the suggested 2-bit multiplier, based on the principle of the constructive and destructive interferences between the input light waves. The results were delivered in graphs containing the transmission level (T) versus an operating wavelength range between 800 and 2000nm, magnetic field distribution, modulation depth (MD), contrast ratio (CR), and insertion loss (IL). The modulation depth was 99.91%, the CR was 14.75dB, and the IL was -1.2d B.

Low-biased probabilistic multipliers using complementary inaccurate compressors

This paper proposes low-biased probabilistic multipliers and applies the proposed designs to the inference stage of convolutional neural networks (CNNs). Highly inaccurate compressors in the probabilistic multiplier make the error distribution unbalanced and produce significant relative errors. We describe design rules for applying different compressors to the probabilistic multiplier. Besides, the proposed design rules enhance the error characteristics by determining the input values of each compressor, suppressing the significant relative error. Notably, motivated by the design rules, we propose a novel inaccurate 4:2 compressor suitable for our new design. The design rules and proposed 4:2 compressor are adopted in 8-bit probabilistic multipliers. The error analysis shows that the new designs can enhance error characteristics without increasing hardware costs. Furthermore, the proposed approximate multipliers are applied to the convolutional layers of CNNs. We describe the fine-tuning scheme to reduce the retraining time of approximation-aware training. The experiments show that proposed designs can produce acceptable classification results compared with those using the floating-point and 8-bit exact multiplications on CIFAR and ImageNet datasets.

A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier

A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA

Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

Reconfigurable stateful logic design in the one-transistor-one-memristor crossbar array for logic-in-memory computing

A reconfigurable stateful logic circuit based on one-transistor-one-memristor (1T1M) crossbar array is proposed by combining the advantages of stateful logic and 1T1M array. Boolean logic operations can be realized not only on the row but also on the column of 1T1M array, which improves the flexibility and computing capability of the array. The same logic circuit can be reconfigured to perform different Boolean logic operations. Then, based on the parallelism of the array and the proposed stateful logic, the 2-bit multiplier and the encryption and decryption circuit of binary images are designed, reducing the logic operating steps. Finally, the circuit simulations of the proposed row-wise logic, the column-wise logic, the 2-bit multiplier as well as the encryption and decryption of SWU binary images are carried out in the 1T1M array. In the proposed stateful logic, the storage of logic inputs, the logic operation process, and the storage of operation results are all executed in 1T1M array, which integrates storage and computation, and effectively overcomes the sneak path problem. The entire scheme provides the application potential of memristor based on two-dimensional materials or conventional materials, opening up a new approach for the next-generation computing.

Approximate 8-bit multipliers and their physical design implementation

Approximate computing is widely used in a large number of error-tolerant applications. Multiplication is an integral arithmetic operation for many of these applications. In this paper we discuss 8 bit multiplier designs designed using approximate 4:2 compressors and encoded sum of partial products, and later introduce an approximate full adder to compute the sum of partial products in less significant bit positions. We use these techniques to systematically trade off accuracy for improvements in area, power and more significantly delay. These multipliers were designed using Verilog and synthesized using Cadence Design Suite with the help of a 45nm standard cell library. The physical designs of exact, existing and proposed multipliers were also performed using the open source RTL to GDS flow tool Q-flow. This is done to highlight the importance and reliability of open source tools in the VLSI physical design process when compared to paid software which may not be accessible to everyone.