1-bit Comparator Research Articles

Retraction Note: Numerical analysis of all optical 1-bit comparator based on PhC structure for optical integrated circuits

Retraction Note: Numerical analysis of all optical 1-bit comparator based on PhC structure for optical integrated circuits

An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology solution for solving CMOS-related issues. The 4-dot squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares 2 voltages or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed 1-bit design employs 35 quantum cells in a 0.04 μm2 compact layout space. Also, the proposed 2-bit design uses 173 cells in a 0.19 μm2 compact layout area. These circuits, which are built across three layers of 90-degree cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented 1-bit comparator circuit uses 3 majority gates with three inputs. The first output signal in 1-bit comparator is generated after 0.75 clock phases and in 2-bit design after 1.25 clock phases. QCADesigner-E evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.

Design and optimization of CMOS based 4-bit comparator

The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits were designed to implement a 4-bit absolute value comparator, each corresponding to one of the rules. Through simulation, calculation, and comparison, the best circuit was identified, providing validation for the rules. The second part of the paper shifts its focus towards optimizing delay and energy consumption by adjusting the sizing of logic gates and the supply voltage to achieve optimal overall performance. In conclusion, further research is needed to corroborate these three rules and identify additional rules, laying the foundation for intelligent circuit optimization.

Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS

Comparators are an important part of the calculator architecture, and rapid advances in semiconductor and electronics technology have placed higher demands on their performance. Optimization of digital systems involves several levels in order to make improvements in their power consumption, delay, and other parameters. This paper designs a low-power, high speed, and area efficient 4-bit absolute-value comparator, which utilizes a static Complementary Metal-Oxide-Semiconductor (CMOS) and Transmission Gate (TG) hybrid structure. The design optimizes the system at the level of separate circuit blocks, logic gates and transistors. The logic functions are realized by means of transcoding and magnitude Comparison, and the input signals are all driven by two-stage inverters. MUX and XOR with excellent performance of TG structure are implemented using simulation and analysis. In this paper, the transistor sizes and supply voltages of each logic gate are calculated and optimized using MATLAB by applying logic effort theory. The design uses a 65nm technology, and transient simulation of the overall system in Cadence successfully realizes its logic functions with 0.83ns delay and 49.6uw power consumption, proving the effectiveness of the design. This study based on theoretical calculations and simulations is a good reference for the design and theoretical study of very large-scale integrated circuits (VLSI).

Optimization and application of numerical comparators in autonomous driving technology

As one of the hot spots in the field of science and technology in recent years, autonomous driving technology is developing rapidly and arousing wide attention. This study explores the application of numerical comparators in autonomous driving technology, with a particular focus on their potential role in environmental perception and decision-making. We have designed and optimized a 4-bit absolute comparator to address the increasing control requirements and energy optimization goals of autonomous vehicles. The results show that numerical comparators play an important role in autonomous driving technology and can be used to quickly and accurately compare sensor data with thresholds, helping systems make critical decisions such as obstacle detection and trajectory planning. By optimizing the circuit design, we managed to reduce energy consumption and achieve the goal of low latency. The significance of this research is to fill the knowledge gap about the application of numerical comparators in automatic driving technology and provide a new idea for the performance improvement of automatic driving system. In the future, we can further explore the innovative potential of numerical comparators in autonomous driving technology to achieve safer, smarter, and more efficient autonomous driving technology.

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

Performance analysis of all-optical 1-bit comparator using 2D-PhC nonlinear ring resonators based on threshold switching method

ABSTRACTIn this research, an all-optical 1-bit comparator (AOCMP) is designed using two-dimensional photonic crystals (2D-PhCs) nonlinear ring resonators (NRRs), and its performance is analyzed based on the threshold switching method. By optimizing the structural parameters of NRRs, such as the refractive index and radius of the rods, this resonator can operate with desired wavelength (1550 nm) within the operating frequency range determined by the transverse magnetic (TM) band diagram. The performance of the proposed AOCMP is analyzed in terms of various factors such as optical switching power, bit rate, time delay, and ON-OFF contrast ratio that are calculated using a finite difference time domain (FDTD) simulation. Also, the operating frequency range (the wavelength range of 1355–2178 (nm)) is investigated using the plane wave expansion (PWE) method. The optimized optical device has exhibited a high contrast ratio of 10.36 dB within a very small size of 325 μm2.

GA evolved CGP configuration data for digital circuit design on embryonic architecture

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

RETRACTED ARTICLE: Numerical analysis of all optical 1-bit comparator based on PhC structure for optical integrated circuits

RETRACTED ARTICLE: Numerical analysis of all optical 1-bit comparator based on PhC structure for optical integrated circuits

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

<p>The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.</p> <p> </p>

A novel proposal for all optical 1-bit comparator based on 2D linear photonic crystal

We employ seven optical waveguides based on two-dimensional linear photonic crystal (LPhC) to realize an all optical comparator (AOCMP). The proposed 1-bit AOCMP has a very simple structure with a footprint of 356 μm2 which is composed of 31 × 33 cubic lattice of silicon rods immersed in air. This LPhC comparator comprises two input ports and two output ports. The functionality of the proposed 1-bit AOCMP is based on constructive and destructive interference phenomenon of optical beams and phase shift keying technique. The finite difference time domain (FDTD) procedure based on Yee’s Algorithm is used to compute the propagation of optical waves in this structure. The FDTD simulation results of suggested 1-bit AOCMP indicate that the minimum and maximum values of the normalized power at ON and OFF states for output ports are 62% and 10%, respectively. Also, the ON–OFF contrast ratio, bit rate, rise and fall times (Tr and Tf) of the suggested design are about 7.92 dB, 2.22 Tb/S, 0.15 ps and 0.05 ps, respectively.

Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis

In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works.

Novel optimized ultra-dense 1-bit magnitude comparator design in quantum-dot cellular automata technology based on MV32 gate

Novel optimized ultra-dense 1-bit magnitude comparator design in quantum-dot cellular automata technology based on MV32 gate

Design and numerical analysis of multifunctional photonic crystal logic gates

All-optical multifunctional structures are at the beginning of the growth and development path to achieve an all-optical integrated circuit (AOIC). The main challenge of designing multifunctional all-optical nanostructures is to maintain the overall function of the structure compared to single-function nanostructures. Simultaneous application of logic gates of AND, XOR, half-adder, 1-bit comparator, reversible Feynman logic gate along with desirable and suitable function are some of the proposed nanostructure properties. The propagation modes in the structure are extracted by the plane wave expansion (PWE) method. The overall operation of the nanostructure, simulation, and numerical analysis of the proposed nanostructure for the submitted applications are performed using the numerical method finite-difference time-domain (FDTD). In the proposed multifunctional nanostructure, ultra-fast and ultra-compact logic gates with a maximum time delay of approximately 280 fs, an area of 104 μm2, and a bit rate of 3.57 Tb/s are provided. In addition to the proposed ultra-compact logic gate, another advantage of the proposed multifunctional nanostructure is achieving the appropriate contrast ratio.

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications.

Efficient designs of high-speed combinational circuits and optimal solutions using 45-degree cell orientation in QCA nanotechnology

To fabricate digital logic circuits withsmaller size, ultra-low power consumption, high-speed, and reliable operation at high frequencies like THz. The quantum-dot cellular automata (QCA) are a novel nanoelectronics nano-technology. It is considered a resolution to the scaling problems in CMOS and VLSI technology. This paper will implement nanoscale-based adder, subtractor, and 1-bit comparator structures using QCA nanotechnology. It is being researched as a possible replacement for traditional CMOS technology. In this paper, we have proposed and investigated the cell rotation problem and provided optimal solutions of 45-degree cell arrangement with its appropriate position. The proposed QCA design effectively reduces the cell count and required area inμm2propagation delay and the complexity of the circuits. The proposed simulation-results of a two-input adder, subtractor, and 1-bit comparator architecture were examined and compared with existing designs using the QCADesigner-E tool. The proposed adder, subtractor and 1-bit comparators occupy design area of 21240.00 nm2 (0.02 um2), 21182.00 nm2 (0.02 um2) and 31284.00 nm2 (0.03 um2) respectively. The observed latency is 0.5 clock cycles for adder and sub, and 0.75 clock cycles for 1-bit comparators. In terms of used equal four-dots QCA cell of 21 cells for adder, sub, and 33 cells for 1-bit comparators circuits with applied synchronized QCA clock cycles methodology. The presented design in this paper will be useful for designing and explaining nano-devices for usage in various nanotechnology applications.

Quantum dot cellular automata using a one-bit comparator for QCA gates

Due to power dissipation, area, and reliability characteristics, CMOS technology has been influenced in nanosystems. Quantum DotCellular Automata(QCA) is a research project that studies alternative feasible systems that have similar capabilities. A 1-bit comparator was constructed using QCA nanotechnology. There are no crossovers in these circuits, making them simple to build. With a range of 74.81 to 99.87 percent improvement in performance, the new design is exceptionally efficient in terms of delay time, cell count, area, and the quantum cost. Thus, offered designs are typically found in different digital logics that demand a minimal amount of area and low power consumption. QCA Designer and QCA Designer E Tool are used to develop and simulate the 1-bit comparator circuits suggested here. The results show that the designed QCA 1-bit circuit requires 0.02 μm2 of area and 16 QCA cells. A delay of 0.5 clock is also obtainable. Compared to the other QCA circuits, the design of the QCA Comparator Circuit improves efficiency, cell count, delay, and cost.

All-Optical Frequency Encoded 2-bit Comparator using Dibit-based logic and Reflective Semiconductor Optical Amplifier

All-Optical Frequency Encoded 2-bit Comparator using Dibit-based logic and Reflective Semiconductor Optical Amplifier

All-optical frequency encoded 2-bit comparator using dibit-based logic and reflective semiconductor optical amplifier

All-optical frequency encoded 2-bit comparator using dibit-based logic and reflective semiconductor optical amplifier