8-bit Arithmetic Logic Unit Research Articles

Design and implementation of an 8-bit ALU based on verilog HDL

Many modern processors incorporate an Arithmetic Logic Unit (ALU) as an integral component. The ALU plays a pivotal role in arithmetic and logical operations, making it a fundamental block in processor architecture. Utilizing software tools like Quartus II and ModelSim, one can seamlessly design, implement, and simulate an 8-bit ALU. This research focuses on creating an ALU that can perform a broad range of operations, including Addition, Subtraction, Multiplication, Division, Shifting, Rotation, AND, OR, XOR, NOR, NAND, XNOR, and Comparison. With these 16 operations in mind, the ALUs circuitry was meticulously crafted using Quartus II. To validate its functionality and performance, joint simulations were conducted with both Quartus II and ModelSim. As a result, comprehensive simulation waveforms were derived, offering insights into the ALUs behavior and response for each instruction. These waveforms serve as a testament to the ALUs robust design and provide a foundation for further analysis and optimization.

Design and Implementation of 12-Bit Arithmetic Logic Unit with 8 Operation Codes to Field Programmable Gate Array

Digital system has been a part of human life since the invention of the computer with a microprocessor as the central brain. At the heart of a processor is an Arithmetic Logic Unit (ALU) that handles arithmetic and logic operations. The need for high-speed computation to handle complex computations demands microprocessors with higher performance. The existing 4-opcode 8-bit ALU cannot handle multiplication operations, so a solution is needed. In this research, while raising the appeal of beginners, a 12-bit ALU with eight operation codes (opcode) was designed and implemented in Xilinx’s Field Programmable Gate Array using a schematic diagram approach through logic gates. The designed and implemented ALU provides addition, subtraction, multiplication, square, AND, OR, NAND, and XOR operations. The multiplication operation was tested by performing the computation to provided datasets to obtain the distance travelled by ten military aircraft based on their maximum speed and air travel duration to ensure its performance. The computation performance comparison with an 8-bit ALU with four opcodes was also done. The computation was done for air travel between 10 to 60 minutes with a 10-minute difference. It was found that the 12-bit ALU with eight opcodes outperformed its contender with computation differences between 130.815 ns and 1,468.214 ns. This high performance is supported by the multiply operation that does repeated addition at one time. Based on this finding, the 8-opcode 12-bit ALU is more efficient in the context of computation time, with consistent accuracy. Moreover, the computation time required to calculate military aircraft data with different maximum speeds and air travel duration is only 119.501 ns.

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.

50 GHz Operation of RSFQ Arithmetic Logic Unit Designed Using the Advanced Design Flow and the Dual RSFQ/ERSFQ Cell Library

Arithmetic Logic Unit (ALU) is an integral part of digital signal processing applications and computing systems. We used ALU, based on Kogge-Stone adder, as a reference circuit to experimentally validate the advanced design flow and the dual RSFQ/ERSFQ standard cell library. Using the advanced design flow, the ALU sub-blocks were optimized across multiple process corners using Monte-Carlo simulations incorporating statistical variations in the process parameters. The correct operation of ALU was verified in the digital HDL simulation using static timing analysis pre-fabrication. We designed the RSFQ 1-bit and 4-bit ALU using the standard cell library approach for MIT-LL 100 µA/µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. For the ERSFQ 1-bit ALU, the bias current overhead for the feeding JTLs was designed to be 100% of the ERSFQ DUT bias current. The RSFQ 1-bit ALU, designed for low frequency functional testing, demonstrated greater than ±15% bias margins. We demonstrated successful operation of the RSFQ 4-bit ALU with greater than ±6% bias margins at 20 GHz, greater than ±5% bias margins at 40 GHz, and greater than ±4% bias margins at 50 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The ERSFQ 1-bit ALU worked up to 30.72 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . In addition, we analyzed the model-to-hardware correlation for the INIT sub-block of the ALU. The simulations accounted for critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ) process parameters. We noted the discrepancy in simulated and measured margins and studied that a 15% higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> in simulations results in better model-to-hardware correlation for the INIT sub-block.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power density of the scaled multi-core architecture. Therefore, it losses reliability features to get overheating and increased temperature. This paper presents a novel power minimization technique for active 4-bit ALU operations using Fin Field Effect Transistor (FinFET) at 22 nm technology. Based on this, a diode is directly connected to the load transistor, and it is active only at the saturation region as a function. Thereby, the access transistor can cutoff of the leakage current, and sleep transistors control the flow of leakage current corresponding to each instant ALU operation. The combination of transistors (access and sleep) reduces the leakage current from micro to nano-ampere. Further, the power minimization is achieved by connecting the number of transistors (6T and 10T) of the FinFET structure to ALU with 22 nm technology. For simulation concerns, a Tanner (T-Spice) with 22 nm technology implements the proposed design, which reduces threshold voltage swing, supply power, leakage current, gate length delay, etc. As a result, it is quite suitable for the ALU architecture of a high-speed multi-core processor.

First-Principles-Based Quantum Transport Simulations of High-Performance and Low-Power MOSFETs Based on Monolayer Ga2O3.

The electronic properties of monolayer (ML) Ga2O3 and transport properties of ML Ga2O3-based n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated by first-principles calculations under the framework of density functional theory (DFT) coupled with the nonequilibrium Green's function (NEGF) formalism. The results show that ML Ga2O3 has a quasi-direct band gap of 4.92 eV, and the x- and y-directed electron mobilities are 1210 and 816 cm2 V-1 s-1 at 300 K, respectively, under the full consideration of phonon scattering. The electron-phonon scattering mechanism shows a temperature-dependent behavior, with the acoustic modes dominating below 300 K and optical modes dominating above 300 K. At a gate length of Lg = 5 nm, the on-current of ML Ga2O3 n-MOSFET for high-performance (HP) application is 2890 μA/μm, which is more than those of the most reported two-dimensional (2D) materials. The delay time as well as the power delay product of ML Ga2O3 MOSFETs can meet the demands of the latest International Technology Roadmap for Semiconductors (ITRS) for HP and low-power (LP) applications until Lg is less than 4 and 5 nm, respectively. Through underlap structure and doping optimization strategies, ML Ga2O3 n-MOSFET can further fulfill the ITRS requirements for 1 nm. At last, we compare the performance of the 32-bit arithmetic logic unit (ALU) built on ML Ga2O3 MOSFETs with the recently reported beyond-CMOS devices. Our results indicate that ML Ga2O3 can serve as a promising channel material in the post-silicon era.

Analysis of an 8-bit Arithmetic Logic Unit using Logisim Emulator

Computers have become an increasingly integral part of our daily lives. This has been a culmination of nearly a century’s work of mathematicians and engineers pushing the boundaries of what machines are capable of doing. Despite the ubiquity and prominence of computers, not many people understand the fundamental components. This is especially important now, as we are on the brink of a fundamental shift in the architecture of computers: from x86-based CPUs to low power, high efficiency RISC/ARM based processors. The technical study conducted below is an attempt to understand CPU functionality as well as search for areas of possible efficiency. This paper will dive in-depth on the fundamentals of computer components through use of early breadboard-type circuitry and the use of LS IC chips, as well as Logisim® simulator to analyze these components, in particular the CPU (Central Processing Unit) and the ALU (Arithmetic Logic Unit).

Based on FS-GDI Approach with 65 nm Technology: Low Power ALU Design

ABSTRACT This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU) utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm node using Cadence Virtuoso simulator. Various ALUI/ALUII designs are presented with different data words. The result of ALUI proves its superiority compared with the traditional CMOS-based design in terms of power consumption, propagation delay and transistor count. The energy of the proposed 4-bit ALU reduced by 32% compared to CMOS based. Scalability of the proposed ALUI and ALUII designs are tested by extending length of the processed bits to 32-bits, through testing the performance of 8-bit, 16-bit, 32-bit ALUs based on the proposed ALUI and ALUII design. It is seen that the energy of the 4-bit ALU reduced by 21.2%, the power efficiency of the DSP and image processing circuits can be improved utilising the proposed designs of the ALUs. The experiment clears the superiority of the proposed ALU units and its suitability for long data words.

Heterocycles: Synthesis, Catalysis, Sustainability, and Characterization

Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-rail overhead, we present an NCL dual-rail/single-rail hybrid system in which single-rail synchronous combinational logic is used between two NCL dual-rail registers. In addition, a 4-bit dual-rail/single-rail hybrid arithmetic logic unit (ALU) and a 4-bit dual-rail ALU are designed to compare performance. To achieve a faster speed, the operation logics in the hybrid ALU adopt transmission gates (TGs). Compared with the 4-bit NCL dual-rail ALU, the 4-bit hybrid ALU (OR operation) has advantages in smaller transistor count (reduced by 14.8%), smaller layout area (reduced by 0.16 mm2), lower power consumption (reduced by 47%), lower delay (reduced by 0.19 ns), and less effect of process/voltage/temperature (PVT) variations. Moreover, the 4-bit NCL dual-rail ALU is optimized with embedded registers in terms of transistor count (reduced by 4%), TASY (reduced by 0.18 ns), and power dissipation (reduced by 0.1 mW).

A dual-rail/single-rail hybrid system using null convention logic circuits

Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-rail overhead, we present an NCL dual-rail/single-rail hybrid system in which single-rail synchronous combinational logic is used between two NCL dual-rail registers. In addition, a 4-bit dual-rail/single-rail hybrid arithmetic logic unit (ALU) and a 4-bit dual-rail ALU are designed to compare performance. To achieve a faster speed, the operation logics in the hybrid ALU adopt transmission gates (TGs). Compared with the 4-bit NCL dual-rail ALU, the 4-bit hybrid ALU (OR operation) has advantages in smaller transistor count (reduced by 14.8%), smaller layout area (reduced by 0.16 mm2), lower power consumption (reduced by 47%), lower delay (reduced by 0.19 ns), and less effect of process/voltage/temperature (PVT) variations. Moreover, the 4-bit NCL dual-rail ALU is optimized with embedded registers in terms of transistor count (reduced by 4%), TASY (reduced by 0.18 ns), and power dissipation (reduced by 0.1 mW).

4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique

4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique

A stable 4-bit ALU design for printed devices

Printed devices fabricated using roll-to-roll (R2R) printing technology have been used in low-cost Internet of Things (IoTs), smart packaging and bio-chips. As the area of applications of printed devices broadens, arithmetic units in digital design need to be implemented. In this paper, we propose a stable 4-bit arithmetic logic unit (ALU) design using a minimum number of transistors that can overcome the limitations of printed devices. We propose the use of a 2:1 transmission gate (TG) multiplexer structure and hybrid 16T full-adder to construct the ALU. New design methods are applied to reduce the number of inverter stages added to overcome the voltage degradation. Using this approach reduces the total number of transistors used in the design from 276 to 153, compared to the conventional design, with significant improvements in delay and power performance.

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

First-principle study of puckered arsenene MOSFET

Two-dimensional material has been regarded as a competitive silicon-alternative with a gate length approaching sub-10 nm, due to its unique atomic thickness and outstanding electronic properties. Herein, we provide a comprehensively study on the electronic and ballistic transport properties of the puckered arsenene by the density functional theory coupled with nonequilibrium Green’s function formalism. The puckered arsenene exhibits an anisotropic characteristic, as effective mass for the electron/hole in the armchair and zigzag directions is 0.35/0.16 m0 and 1.26/0.32 m0. And it also holds a high electron mobility, as the highest value can reach 20 045 cm2V–1s–1. Moreover, the puckered arsenene FETs with a 10-nm channel length possess high on/off ratio above 105 and a steep subthreshold swing below 75 mV/dec, which have the potential to design high-performance electronic devices. Interestingly, the channel length limit for arsenene FETs can reach 7-nm. Furthermore, the benchmarking of the intrinsic arsenene FETs and the 32-bit arithmetic logic unit circuits also shows that the devices possess high switching speed and low energy dissipation, which can be comparable to the CMOS technologies and other CMOS alternatives. Therefore, the puckered arsenene is an attractive channel material in next-generation electronics.

Ballistic Transport in High-Performance and Low-Power Sub-5 nm Two-Dimensional ZrNBr MOSFETs

Here, the electronic properties and ballistic transport properties of two-dimensional (2D) ZrNBr are comprehensively investigated by the nonequilibrium Green’s function coupled with density functional theory. 2D ZrNBr has a wide direct band gap of 1.82 eV with the highest mobility of 8700cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ . Both the n- and p-type 2D ZrNBr MOSFETs with 5-nm channel length hold the on-currents above $2300~\mu \text{A}/\mu \text{m}$ for high-performance devices and an on/off ratio exceeding 106 for low-power applications, which is of great value for the design of complementary circuits in 2D electronics. In addition, the energy-delay products of the single 2D ZrNBr MOSFETs and the 32-bit Arithmetic Logic Unit show more potential compared to other 2D materials and CMOS proposals. Thus, this work broadens a promising path towards beyond-silicon electronic systems.

Electronic-photonic arithmetic logic unit for high-speed computing

The past two decades have witnessed the stagnation of the clock speed of microprocessors followed by the recent faltering of Moore’s law as nanofabrication technology approaches its unavoidable physical limit. Vigorous efforts from various research areas have been made to develop power-efficient and ultrafast computing machines in this post-Moore’s law era. With its unique capacity to integrate complex electro-optic circuits on a single chip, integrated photonics has revolutionized the interconnects and has shown its striking potential in optical computing. Here, we propose an electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits. We experimentally demonstrate its practicality by implementing a 4-bit arithmetic logic unit consisting of 8 high-speed microdisk modulators and operating at 20 GHz. This approach paves the way to future power-saving and high-speed electronic-photonic computing circuits.

Magnetic Logic Gate Based on Polarized Spin Waves

Spin wave, the precession of magnetic order in magnetic materials, is a collective excitation that carries spin angular momentum. Similar to the acoustic or optical waves, the spin wave also possesses the polarization degree of freedom. Although such polarization degrees of freedom are frozen in ferromagnets, they are fully unlocked in antiferromagnets or ferrimagnets. Here we introduce the concept of magnetic gating and demonstrate a spin wave analog of the Datta-Das spin transistor in antiferromagnet. Utilizing the interplay between polarized spin wave and the antiferromagnetic domain walls, we propose a universal logic gate of pure magnetic nature, which realizes all Boolean operations in one single magnetic structure. We further construct a full functional 4-bit Arithmetic Logic Unit using only sixteen spin wave universal logic gates, operating in a weaving fashion as a Jacquard loom machine. The spin wave-based architecture proposed here also sets a model for the future energy efficient non-volatile computing, the distributed processing-in-memory computing, and the evolvable neuromorphic computing.

Design of 8-Bit ALU Design using GDI Techniques with Less Power and Delay

Arithmetic Logic Unit (ALU) is a substantial fragment of microchip. Cutting-edge computerized processors, legitimate and math activity accomplishes making use of ALU. This paper depicts an 8-Bit ALU operating with a lowest power 11-Transistor Full Adder (11-T FA) and Gate dispersion input (GDI) centered MUX. All structures were simulated using Tanner EDA software version-15 with 32 nanometer BSIM4 innovation. Execution examinations were furnished as for voltage, power, postponement and power delay item. In this paper 8-bit ALU operated in subthreshold region, selected 0.7 VDD for maintain the both power as well as delay. In 8-bit ALU of GDI proposed model, less than 82% power consumption reduced as compare with CMOS 8-Bit ALU due to voltage level improvement.

A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption.

ERSFQ 8-Bit Parallel Arithmetic Logic Unit

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.