6T Static Random Access Memory Cell Research Articles

Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications

The rapid proliferation of Internet of Things (IoT) devices has escalated the demand for energy-efficient memory solutions. The development of SRAM (Static Random-Access Memory) has gathered significant attention, particularly for low-power applications and portable devices. This research introduces a novel approach to ensure robust performance and operational integrity, all while adhering to stringent power constraints amidst process and temperature fluctuations. This quest for alternative nano-devices has been ignited by the scaling and channel control challenges intrinsic to CMOS technology. Among the array of alternatives, including FinFETs, TFETs, and CNTFETs, FinFETs have emerged as strong contenders. FinFET SRAMs contribute to the ongoing drive for electronic devices to become more compact and energy-efficient. They offer a distinct advantage as a promising CMOS substitute, attributed to their high performance, stability, with low power consumption characteristics at the nanoscale. The study proposes an ultra-low power 9T FinFET based SRAM cell meticulously designed for IoT applications. Leveraging the unique attributes of FinFET based 9T cell, the proposed SRAM cell is tailored to achieving minimal power consumption while maintaining inherent stability. The study assesses the performance of the proposed SRAM cells for power dissipation, stability, speed, and energy efficiency, and compares them with existing SRAM structures. The results are obtained through the Monte Carlo simulation technique, which evaluates circuit performance under specified conditions. The study achieves remarkable efficiency gains with 9T SRAM cells compared to other configurations. Additionally, the reduced read and write access times facilitate expedited data retrieval and storage operations.

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

Radiation tolerant capacitor-SRAM without area overhead

In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Circuit-level design of radiation tolerant memory cell

As transistors shrink in size, the integration density of memory circuits like Static Random Access Memory (SRAM) cells rises, making them increasingly susceptible to Single Event Effects (SEE). In the space environment, memory circuits face stability and reliability challenges due to the presence of various charged particles such as α-particles, neutrons, electrons, heavy ions, and photons. These high-energy particles create ion tracks when they strike the memory device, leading to upsets in the storage bits. Conventional 6 T SRAM cells are susceptible to these upsets. As a solution this paper proposes a new Radiation Tolerable (RT 13 T) SRAM cell that is better suited for deep-space applications compared to other memory cell. RT13T has been validated to withstand radiation hazards through Critical Charge (QCrit) analysis, which shows that it exhibits 1.17×, 1.1×, 1.94× and 1.06× highest QCritthan QUCCE 10 T/12 T,traditional 6 T and LIOR 13 T memory cells, respectively. As the comparison made, our Proposed RT 13 T saved by5.1 %,9.9 %, 20.1 % and 7 % of the power consumption compared to QUCCE10T/12 T/LIOR 13 T/SERSC-16 T SRAM cells at a nominal supply voltage of 0.7 V. It also exhibits shorter read delay (TRA) 10.6 %, 1.34 %, 9.6 %, 22.16 %compared to QUCCE 10 T/12 T,6T, SERSC-16Tmemory cells, respectively. In terms of stability,our proposed RT13T SRAM cell exhibits 2.32×/2.05×/2.9×/1.05×/1.01 × higher read stability as compared with QUCCE10T/12 T/6T/LIOR 13 T/SERSC-16 T memory cells during the read operation. The our proposed RT13T shows improvements in design metrics are at the expense of a longer write delay. To characterize the performances of the proposed RT13T, 16-nm CMOS predictive technology model and validated through extensive simulation with licensed PrimeSim HSPICE of Synopsys. The results of our proposed RT13T cell are compared with some other previously proposed memory cells such as 6 T, QUCCE 10 T, QUCCE 12 T, LIOR 13 T and SERSC-16 T memory cells. The obtained results are tabulated and plotted for graphical analysis. In terms of area consumption our proposed 13 T consumes 0.9×/0.6 × lesser area than QUCCE 12 T/SERSC-16 T memory cells but our proposed circuit consumes 3.1×/1.08×/1.05 × more area than QUCCE10T/conventional 6 T/LIOR 13 T because QUCCE10T and 6 T consist of less number of transistors in memory cells.The cell proposed in this paper demonstrates strong radiation-hardened capabilities and excellent overall performance, making it well-suited for aerospace electronic devices and ensuring stable operation in space radiation environments.

Comprehensive Study of Low-Power SRAM Design Topologies

Abstract: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Performance of 9T SRAM Cell using Boolean algebra and Arithmetic Operations

This work aims to implement the Boolean and Arithmetic functions with Static Random Access Memory (SRAM) Cell made by nine CMOS Transistor for In-Memory computation. Normally the Von-Neumann architecture is used for current computing system where data and programs are placed in a single memory by sharing and a single Bus is used for memory access, ALU and for controlling of program. This results in minimizing the efficiency of computing when there is high eminence on Data tactless applications. The Von-Neumann architecture is made more efficient by Computation in Memory (CIM) architecture which overcome the drawback of Memory barrier, the power utilization and in the resemblance of wall structure. Here is presented an inside the memory computation method and co-designs of arithmetic circuitry using 9T SRAM cell. The Boolean algebra and Arithmetic operations are illustrated with 9T SRAM cell designed by CMOS technology in 180 nm process. The Boolean algebra for AND- NAND, OR-NOR logic gates are illustrated using 9T SRAM cells with the Latch type sense amplifier to verify the capability of computation in Memory of 9T SRAM cell. To illustrate the arithmetic circuit an array of memory has been made by the 9T SRAM cell and proposed sensing amplifier which is latch type and finally is mapped with circuit of half-adder and half-subtraction.

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18 nm technology.

Expanded Noise Margin 10T SRAM Cell using Finfet Device

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential.

Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller

Researchers in the field of device research are always searching for a device that meets certain criteria, such as having low leakage and a low threshold voltage, without sacrificing performance. This pursuit has led to the development of numerous gate architectures. As a result of the enormous size of the static random-access memory (SRAM), its yield and leakage power consumption account for the majority of the chip’s total yield and leakage power consumption respectively. However, as CMOS technology continues to grow in the sub-65 nanometer domain to lower the cost of transistors and the dynamic power, it presents a number of issues on the design of SRAM. In this paper, a 6T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 6T cell which uses high and low VTH transistors to improve the read and write stability. Also, the changes of cell parameters when the temperature rises from 40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell are studied at two supply voltages of 400 mV and 500 mV.

Improved reliability single loop single feed 7T SRAM cell for biomedical applications

Portable biomedical devices are born to reach a maximum number of people at an effective cost, and because of their small size and battery operation, the impact of portable medical devices is huge. For biomedical image processing devices, it is very important to store pixel information in embedded memory, because pixel values contain critical information about the image. For this critical information storage, most embedded memories consist of static random access memory (SRAM). SRAM, which stores critical information must have a high level of stability and reliability with low power dissipation. This paper proposes a single loop single-feed 7T (SLSF7T) SRAM cell that operates in the sub-threshold region (reducing the supply voltage to reduce power dissipation) and attains a high read static margin. To evaluate the read-and-write stability of the SRAM cell, the N-curve method is adopted in this work.The proposed SLSF7T SRAM cell design offers several improvements over existing Biomedical Transmission Gate 8T (BT8T) and 9T SRAM cells. Specifically, the SLSF7T SRAM cell design shows an increase in static voltage noise margin (SVNM) by 75.86% and 75.34%, reduction in delay by 37.86% and 58.52%, and also offers less leakage power dissipation by 72% and 23.29% as compared to the BT8T and 9T cells, respectively. Along with the low power and high stability, the other most significant feature of the proposed work is its area efficiency because the proposed memory cell only consists of 7 transistors, it requires only 1.1X area overhead compared to the conventional 6T memory cell. The calculated performance matrix of the proposed cell is the highest among the considered SRAM cells for compression. The proposed cell operates in the sub-threshold region and achieves the best performance parameters for memory design for biomedical devices and applications at a 300 mV supply voltage.

A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS

Abstract: Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

Compute-in-memory (CiM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, the tradeoff between energy efficiency and computing precision plagues most CiM implementations, and the low precision imposes a major limitation on CiM’s ability to support practical computational workloads. In this article, a static random access memory (SRAM)-based analog CiM macro is presented with the Intel 22FFL process. By introducing a 1-to-2 ratioed capacitor ladder (C-2C)-based charge domain computing scheme, the proposed CiM prototype chip demonstrates a maximum of 2k multiply-accumulate (MAC) operations in one clock cycle and achieves 32.2-TOPS/W peak power efficiency with 8-bit precision in both input activation and weight while ensuring accurate on-chip matrix–vector multiplications (MVMs) with a computation error less than 0.5%. A 4.0-TOPS/mm2 peak area efficiency is attained by adopting a local weight multiplexing scheme with a 9T SRAM cell, which improves the memory density and reduces the need to refresh the weight stored in the SRAM array. A variety of analog impairment factors, including parasitics, mismatch, and noise, were analyzed to guarantee a sufficiently high multibit linearity. The proposed passive analog computing mechanism ensures the computation accuracy over process–voltage–temperature (PVT), with the measured MVM error deviation of less than 1% over PVT variations.

Ultra-low leakage static random access memory design

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Performance Analysis Of SRAM and Dram in Low Power Application

All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications

ABSTRACT Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs.