6T Static Random Access Memory Research Articles

Comprehensive Study of Low-Power SRAM Design Topologies

: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

Design of reliable and fast Schmitt trigger 10T SRAM cells using in-memory computing

Abstract Microprocessors, integrated data storage systems, and cache memories are just a few applications that can benefit from Static random access memory (SRAM). Computing In memory provides a solution for the von Neumann bottleneck problems. Simultaneously, it removes needless repeated data transmission between CPU and memory. Schmitt trigger was utilized for energy-efficient operation to get high reading and writing capacity. Two cross-coupled inverters with a transistor in between increase the design writing process. Furthermore, voltage boost logic is prioritized to maximize the node capacity. Using two dummy columns and dummy rows in RAM, the Replica technique controls the flow of signals via the core. The simulated results are compared to the designs that already exist. The simulation results show that the leakage power of the proposed design is 0.75 nw at 0.6 volts. The write static noise margin (WSNM) of the proposed cell is twice that of SEDF10T, which can be helpful for high-performance computing applications.

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

A FinFET based Low Leakage 10T Static Random Access Memory cell

A FinFET based Low Leakage 10T Static Random Access Memory cell

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Abstract To meet industry requirements of higher transistor count SRAM cells this paper is proposing, a nine-transistor configuration static random access memory (SRAM) cell which is accessible by dual bit line and performing simultaneous read and write operations. The suggested 9T (P9T PS) cell is constructed at 32 nm CMOS and is operating at an operating voltage 0.9 V. To justify the refined performance of proposed design various analysis are carried out that shows the static noise margins (SNM) that occurs while executing the read operation is 0.368 V and hold operation by the cell is 0.364 V, while the write operation has an SNM of 0.422 V. The access time for write and read functions of the cell is found to be 1.2 nS and 4.5 nS respectively. The P9T PS SRAM is compared with other dual-port and single-port 9T SRAM cells is stand out to be pre-eminence in performance in terms of noise immunity, temperature variations, power consumption (static and dynamic both), power delay product (PDP), SNM to PDP and area ratio (SAPR) and electric quality matric. Total leakage power for P9T PS cell is found to be 22.1 nW. The P9T PS bit cell is also found to be power efficient as it is consuming minimal power for all of the operations. Area layout of the P9T (PS) is found to be 22.372 μm2. The results are also supported by the process corner variation analysis for four different corners. LT-spice software is used to carry out all the simulations and analysis.

Efficient turbo product code decoder with Build‐In SRAM‐based transpose memory

AbstractTurbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz.

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

Ultra8T: A sub-threshold 8T SRAM with leakage detection

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 μs read delay, and the minimum energy required is 1.69 pJ at 0.4 V

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

This study examines the operational parameters of field-effect transistors (FETs) using single-gate (SG) and double-gate (DG) graphene nanoribbons (GNRs) within the analog/RF domain. A detailed exploration is conducted through an atomistic pz orbital model, derived from the Hamiltonian of graphene nanoribbons, employing the nonequilibrium Green’s function formalism (NEGF) for analysis. The atomic characteristics of the GNRFETs channel are accurately described by utilizing a tight-binding Hamiltonian with an atomistic pz orbital basis set. The primary focus of the analysis revolves around essential analog/RF parameters such as transconductance, transconductance generation factor (TGF), output resistance, early voltage, intrinsic gain, gate capacitance, cut-off frequency, and transit time. Furthermore, the study assesses the gain frequency product (GFP), transfer frequency product (TFP), and gain transfer frequency product (GTFP) to evaluate the balance between transistor efficiency, gain, and cut-off frequency. The research outcomes indicate that double-gate GNRFETs exhibit superior analog/RF performance in comparison to their single-gate counterparts. However, both types of devices demonstrate cut-off frequencies in the gigahertz range. The extensive data presented in this study provides valuable insights into the characteristics of SG and DG GNRFETs, particularly in terms of the figure-of-merit (FoM) for analog/RF performance, offering a comprehensive analysis of the trade-offs in analog applications. In addition, the analysis has been extended be performing a high-performance hybrid 6T static random-access memory (SRAM) to get the impact in their circuit level variation as well as improvement in their circuit performance.

Ultra-Low Power 9T FinFET Based SRAM Cell for IoT Applications

The rapid proliferation of Internet of Things (IoT) devices has escalated the demand for energy-efficient memory solutions. The development of SRAM (Static Random-Access Memory) has gathered significant attention, particularly for low-power applications and portable devices. This research introduces a novel approach to ensure robust performance and operational integrity, all while adhering to stringent power constraints amidst process and temperature fluctuations. This quest for alternative nano-devices has been ignited by the scaling and channel control challenges intrinsic to CMOS technology. Among the array of alternatives, including FinFETs, TFETs, and CNTFETs, FinFETs have emerged as strong contenders. FinFET SRAMs contribute to the ongoing drive for electronic devices to become more compact and energy-efficient. They offer a distinct advantage as a promising CMOS substitute, attributed to their high performance, stability, with low power consumption characteristics at the nanoscale. The study proposes an ultra-low power 9T FinFET based SRAM cell meticulously designed for IoT applications. Leveraging the unique attributes of FinFET based 9T cell, the proposed SRAM cell is tailored to achieving minimal power consumption while maintaining inherent stability. The study assesses the performance of the proposed SRAM cells for power dissipation, stability, speed, and energy efficiency, and compares them with existing SRAM structures. The results are obtained through the Monte Carlo simulation technique, which evaluates circuit performance under specified conditions. The study achieves remarkable efficiency gains with 9T SRAM cells compared to other configurations. Additionally, the reduced read and write access times facilitate expedited data retrieval and storage operations.

Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies

Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing in terms of Cell ratio and Pull up ratio on stability margins of designed SRAM topologies. Simulations are carried out in the HSPICE environment using 16 nm and 22 nm CMOS process nodes. We find that the stability margins of 10T SRAM cell outperform the 6T SRAM cell; however stability margin decreases with decreasing technology nodes. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) of 10T SRAM cell is improved by 48.38% and 308.64% respectively in 22nm and 53.04% and 243.93% respectively in 16nm process technology as compare to 6T SRAM cell.

Radiation tolerant capacitor-SRAM without area overhead

In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Circuit-level design of radiation tolerant memory cell

As transistors shrink in size, the integration density of memory circuits like Static Random Access Memory (SRAM) cells rises, making them increasingly susceptible to Single Event Effects (SEE). In the space environment, memory circuits face stability and reliability challenges due to the presence of various charged particles such as α-particles, neutrons, electrons, heavy ions, and photons. These high-energy particles create ion tracks when they strike the memory device, leading to upsets in the storage bits. Conventional 6 T SRAM cells are susceptible to these upsets. As a solution this paper proposes a new Radiation Tolerable (RT 13 T) SRAM cell that is better suited for deep-space applications compared to other memory cell. RT13T has been validated to withstand radiation hazards through Critical Charge (QCrit) analysis, which shows that it exhibits 1.17×, 1.1×, 1.94× and 1.06× highest QCritthan QUCCE 10 T/12 T,traditional 6 T and LIOR 13 T memory cells, respectively. As the comparison made, our Proposed RT 13 T saved by5.1 %,9.9 %, 20.1 % and 7 % of the power consumption compared to QUCCE10T/12 T/LIOR 13 T/SERSC-16 T SRAM cells at a nominal supply voltage of 0.7 V. It also exhibits shorter read delay (TRA) 10.6 %, 1.34 %, 9.6 %, 22.16 %compared to QUCCE 10 T/12 T,6T, SERSC-16Tmemory cells, respectively. In terms of stability,our proposed RT13T SRAM cell exhibits 2.32×/2.05×/2.9×/1.05×/1.01 × higher read stability as compared with QUCCE10T/12 T/6T/LIOR 13 T/SERSC-16 T memory cells during the read operation. The our proposed RT13T shows improvements in design metrics are at the expense of a longer write delay. To characterize the performances of the proposed RT13T, 16-nm CMOS predictive technology model and validated through extensive simulation with licensed PrimeSim HSPICE of Synopsys. The results of our proposed RT13T cell are compared with some other previously proposed memory cells such as 6 T, QUCCE 10 T, QUCCE 12 T, LIOR 13 T and SERSC-16 T memory cells. The obtained results are tabulated and plotted for graphical analysis. In terms of area consumption our proposed 13 T consumes 0.9×/0.6 × lesser area than QUCCE 12 T/SERSC-16 T memory cells but our proposed circuit consumes 3.1×/1.08×/1.05 × more area than QUCCE10T/conventional 6 T/LIOR 13 T because QUCCE10T and 6 T consist of less number of transistors in memory cells.The cell proposed in this paper demonstrates strong radiation-hardened capabilities and excellent overall performance, making it well-suited for aerospace electronic devices and ensuring stable operation in space radiation environments.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Performance of 9T SRAM Cell using Boolean algebra and Arithmetic Operations

This work aims to implement the Boolean and Arithmetic functions with Static Random Access Memory (SRAM) Cell made by nine CMOS Transistor for In-Memory computation. Normally the Von-Neumann architecture is used for current computing system where data and programs are placed in a single memory by sharing and a single Bus is used for memory access, ALU and for controlling of program. This results in minimizing the efficiency of computing when there is high eminence on Data tactless applications. The Von-Neumann architecture is made more efficient by Computation in Memory (CIM) architecture which overcome the drawback of Memory barrier, the power utilization and in the resemblance of wall structure. Here is presented an inside the memory computation method and co-designs of arithmetic circuitry using 9T SRAM cell. The Boolean algebra and Arithmetic operations are illustrated with 9T SRAM cell designed by CMOS technology in 180 nm process. The Boolean algebra for AND- NAND, OR-NOR logic gates are illustrated using 9T SRAM cells with the Latch type sense amplifier to verify the capability of computation in Memory of 9T SRAM cell. To illustrate the arithmetic circuit an array of memory has been made by the 9T SRAM cell and proposed sensing amplifier which is latch type and finally is mapped with circuit of half-adder and half-subtraction.

A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.

In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block

A possible approach to overcome the von Neumann bottleneck and meet the increasing demand for better computing performance is to computing in-memory (CIM). The results of the in-memory calculations are primarily reflected in the vertical bitline (BL) analog voltage. However, the nonlinearity of the BL discharge deteriorates with the increase in discharge voltage. In this study, we propose a diagonal symmetry weight block (DSWB) based on an eight-transistor (8T) static random access memory (SRAM) that can achieve multibit transposable operations. In addition, to guarantee linearity and complete multibit multiplication operations, we propose a cascode current mirror (CCM)-based multiplier. To achieve low-overhead and more efficient quantification, our proposed CIM macro uses a counter-type quantization circuit to read out the analog calculation results. We simulated the performance of the proposed 8T SRAM in a 28-nm complementary metal–oxide–semiconductor process. The integral nonlinearity (INL) of the proposed CCM-based CIM decreased by approximately 54.4% compared with the traditional CIM. Furthermore, the proposed in-memory multibit multiplication throughput density was 6.74 GOPS/kb; this throughput density improvement is approximately 3.3–10.5 times higher than the existing CIM works.