65nm CMOS Research Articles

A Fully-Integrated 60-GHz 8-Element Phased-Array Transceiver with Embedded Antenna T/R Switch in 65-nm CMOS

This paper presents an 8-element phased-array heterodyne transceiver (TRX) chip for 60-GHz wireless applications. The chip integrates transmit/receive (T/R) elements, bi-directional variable-gain driving amplifiers (BI-VGDAs), up/down mixing chains, and the local oscillator (LO) chain. To support the time division duplexing (TDD) operation and increase output power, a low-loss compact on-chip antenna T/R switch is introduced by embedding it in the power amplifier (PA) power combiner, thereby achieving a high transmitter (TX) output power and low receiver (RX) noise figure (NF), respectively. Fabricated in a 65-nm CMOS process, the proposed phased array TRX chip occupies an area of 5.1 mm×2.5 mm. With measurements, the TX path provides a 32-dB maximum conversion gain, an 11.3-dBm OP1dB, and a 16-dBm Psat, respectively. The RX path achieves a peak gain of 24 dB and an NF of 6.5-9 dB across 57-66 GHz. With the 16-QAM modulation, a 7.04 Gb/s data rate is demonstrated.

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

Radiation Hardened Read-Stability and Speed Enhanced SRAM for Space Applications

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications.

A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs

This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (Vi,cm) range. The proposed comparator has high-speed performance throughout the 0-Vdd Vi,cm range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail Vi,cm operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the Vi,cm value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different Vi,cm.

A 132–170 GHz high-gain driving amplifier utilizing asymmetric broadside coupled line in 40-nm CMOS

This paper presents a driving amplifier (DA) utilizing the proposed asymmetric broadside coupled line. In contrast to conventional coupled line, the balun devised with proposed asymmetric coupled line and enhanced wideband balance compensation technique is utilized, thereby achieving wideband impedance matching and mitigating insertion loss. Additionally, the utilization of the lossy over-neutralization technique substantially enhances the power gain of amplifiers operating in the upper millimeter-wave band (150 GHz–300 GHz). The DA is fabricated utilizing a 40-nm CMOS process without aluminum layers. The fabricated amplifier demonstrates a compact total area of 0.135 mm2 (0.031 λ2), with a core area of 0.027 mm2 (0.0061 λ2). It achieves a high gain of 19.4 dB, high power of 11.05 dBm, and high power-added efficiency (PAE) of 11.05% at 160 GHz. Moreover, both the 3-dB power gain bandwidth and the 3-dB saturated power bandwidth extend from 132 GHz to 170 GHz, covering a bandwidth of 38 GHz. This configuration underscores the robust performance of the DA in the upper millimeter-wave band.

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS

A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS

A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS

With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.

0.765-FJ/Bit/Search Content Addressable Memory Using Search Line Pre-Charge-Free (SLPF) Scheme

Content Addressable Memories (CAMs) are high-speed hardware lookup tables that are crucial in routing, packet classification, search, and other fast look-up applications. Despite having the advantage of high speed, they have limitations due to their power hungriness. This paper addresses the limitations of existing CAMs with two novel modifications in the proposed Search Line Pre-Charge-Free Low-Power-Content Addressable Memory (SLPFCAM) structure. The first novelty is their gated evaluation matching circuit and the second is a match line pre-charge controller. The proposed design reduces the energy consumption and improves the speed of the CAM by eliminating the SLprecharge phase in the CAM operation. The pre-charge controller prevents the attempt of match line pre-charge when it is not required. The design has been implemented using Cadence Virtuoso in a 90-nm CMOS technology with 1-V supply, and the post-layout simulation results show that the SLPFCAM makes significant improvements with a minimum of 83% less power consumption, a 91% less search delay, and the average energy consumption being 0.765 fJ/bit/search.

Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review

Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

An exponential variation based PSO for analog circuit sizing in constrained environment

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, ζ1 and ζ2, into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters ζ1 and ζ2 in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

A 1024-Channel Simultaneous Electrophysiological and Electrochemical Neural Recording System with In-Pixel Digitization and Crosstalk Compensation.

Simultaneous electrophysiological and chemical recording allows for multi-modal neural instrumentation and provides insights into chemical synapses and ion channels across the cell membrane. However, intermodal interference can hinder highly synchronized recording in large-scale systems with high temporal and spatial resolution. In this work, we propose a 1024-channel lab-on-CMOS system for dual-modal neural recording with in-pixel digitization and interference suppression. A foreground calibration scheme with tunable capacitance is implemented in-pixel to compensate for the crosstalk between electrical and chemical recording. Active pixels for both electrical and chemical modalities are designed based on a pulse width modulation (PWM) analog-to-digital conversion scheme. CMOS-compatible post-processing is implemented to realize in-pixel electrodes and chemical sensing membranes. The prototype, implemented in a 180nm CMOS technology, occupies a total area of 33mm2 with 1024 pixels, and each unit pixel includes one electrical recording site and two chemical recording sites, with dimensions of 150μm×130 μm. The total system power consumption is 19.68mW at a frame rate of 9k and 3k for electrical and chemical imaging respectively. The in-vitro experiment demonstrated the concurrent high density electrophysilogical and electrochemical recording with sub millisecond temporal resolution.

A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC

In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively.

A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad

A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad

A 10-bit 70-MS/s SAR ADC with Reference Buffer in 40nm CMOS

Abstract A 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with reference buffer is presented in this paper. Segmented capacitive DAC with redundant 2bits is designed to relax the design of reference buffer. A hybrid switching sequence is applied to the ADC to optimize power consumption. The Measurement results Show that the core SAR ADC achieves 48.52 dB SNDR and 56.67 dB SFDR at 70 MS/s sampling rate and Nyquist input frequency, consuming 2.50mW power consumption, achieving a FoM of 163.6 fJ/step. The ADC occupies an active area of 0.017 mm2 in 40nm CMOS technology.

A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS

A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS

A CMOS front-end circuit for capacitive sensors with zero adjustment

A front-end circuit with measurement zero adjustment was designed using 180nm CMOS technology for capacitive sensors. A series-switched capacitor composed of capacitor under test and MOSFETs is controlled by a clock signal to convert capacitance to current. The minimum output current at fixed capacitance can be adjusted by applying different voltage to realize zero adjustment. The test shows that the output current has a monotonic linear relationship with the measured capacitance, with capacitance detection range reaches 50pF-3000pF and an output current range of 0.59mA-22.2mA. The maximum span of multiple measurements was lower than 8.37uA. The stable time is less than 23ms and sensitivity is 19.8uA/pF. This circuit is suitable for long-distance and wide-range capacitance detections.

A Calibration Scheme for a 800-Ms/s 14 Bit Pipelined ADC in 28-nm CMOS

Abstract A calibration scheme is proposed to compensate linear and nonlinear errors including offset, cap mismatch, second- and higher-order harmonics and memory induced errors in pipelined analog-to-digital converters (ADCs). The alternating minimization (AM) algorithm is proposed to accurately estimate the coefficients of the errors. As an accurate input value is hardly acquired in practical measurements, instead, the proposed scheme estimates the input and the error coefficients jointly. Once the error coefficient was calculated, it will be recorded in a lookup table (LUT). The scheme has been demonstrated in a 800-Ms/s 14-bit pipelined ADC fabricated in a 28nm CMOS process, which features a signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) improvement of 2.49 dB and 11.49 dB at 800-Ms/s.

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.