65nm Technology Research Articles

Design of High Performance and Power Efficient Flash ADC

In this paper, Flash Analog to digital converter is implemented. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Here, we are modifying the structure of operational Amplifier using Power Gating Technique. Binary code is obtained from the thermometer code by utilizing a Mux based encoder by designing the MUX in domino Logic. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the propagation delay of the ADC by optimizing encoder circuitry. With the purpose of reducing latency, Encoder is implemented using 2:1 mux based on Pseudo NMOS Logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.

Tolerance of Siamese Networks (SNs) to Memory Errors: Analysis and Design

This article considers memory errors in a Siamese Network (SN) through an extensive analysis and proposes two schemes (using a weight filter and a code) to provide efficient hardware solutions for error tolerance. Initially the impact of memory errors on the weights of the SN (stored as floating-point (FP) numbers) is analyzed; this shows that the degradation is mostly caused by outliers in weights. Two schemes are subsequently proposed. An analysis is pursued to establish the filter's bounds selection by the maximum/minimum values of the weight distributions, by which outliers can be removed from the operation of the SN. A code scheme for protecting the sign and exponent bits of each weight in an FP number, is also proposed; this code incurs in no memory overhead by utilizing the 4 least significant bits (LSB) to store parity bits. Simulation shows that the filter has a better performance for multi-bit errors correction (a reduction of 95.288% in changed predictions), while the code achieves superior results in single-bit errors correction (a reduction of 99.775% in changed predictions). The combined method that uses the two proposed schemes, retains their advantages, so adaptive to all scenarios; The ASIC-based FP designs of the SN using serial and hybrid implementations are also presented; these pipelined designs utilize a novel multi-layer perceptron (MLP) (as branch networks of the SN) that operates at a frequency of 681.2 MHz (at a 32nm technology node), so significantly higher than existing designs found in the technical literature. The proposed error-tolerant approaches also show advantages in overheads comparing with for example traditional error correction code (ECC). These error-tolerant MLP-based designs are well suited to hardware/power-constrained platforms.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

Design of Low Power Low Offset Dynamic latch Comparator using DTMOS Technique

Analog to Digital converters plays an essential role in signal processing and medical applications. SAR ADC is best suited for biomedical applications because of its low power and medium resolution. Low power dynamic comparators are essentially desired in the design of SAR ADC. In this paper, a low power dynamic type latch comparator is designed which is based on Dynamic Threshold Metal Oxide Semiconductor (DTMOS ) technique to reduce the power dissipation which is achieved by reducing the supply voltage. The circuit has been implemented at the supply voltage of 0.8 V. The simulations for this comparator are carried out in CADENCE SPECTRE using 45nm CMOS technology. The simulation outcomes validate that the designed dynamic latch comparator with DTMOS techniques is 20% more power saving in comparison to the conventional comparator. The total power consumption is as low as 156.18nW which makes it suitable for low-power bio-medical applications.

Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT

Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3–3.55 V with an input 1–1.5 V with a power throughput of 0–22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.

Design and Simulation of Low Dropout, Low Power Capless Linear Voltage Regulator

This paper demonstrates a low power, frequency compensated with on-chip capacitor, low dropout linear voltage regulator. The proposed low dropout regulator (LDO) delivers a constant output voltage of 2.4[Formula: see text]V for an input range of 2.5–6.8[Formula: see text]V. A minimal drop of 2[Formula: see text]mV and 20[Formula: see text]mV was observed at no load and full load output current of 0 A to 100[Formula: see text]mA, respectively. LDO is realized by a high-gain two-stage error amplifier, internally compensated by passive a high-pass filter to achieve stability over a load current range of 0–100[Formula: see text]mA without occupying as much area as an active high-pass filter. The LDO presented requires a bias current of 10[Formula: see text]mA with a reference voltage of 1.5[Formula: see text]V and is designed in 180-nm technology.

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Design and simulation of 7 GHz CMOS wideband amplifier(CMOSWA) using a modified cascode circuit realized in 90-nm CMOS technology is presented here. The proposed system consists of two stages, namely a modified folded cascode and an inductively degenerated common source amplifier. The circuit is experimented with and without a feedback network. This work discusses the performance variation as a function of reactive components, and the initial stage results in 22 dB gain,2.6 GHz bandwidth, and 40GHz unity gain-bandwidth. The circuit without the feedback network exhibits 30.7dB gain,4.8GHz bandwidth(BW), and 10GHz unity-gain bandwidth(UGB). The reactive feedback network's inclusion helped to achieve 38.7 dB gain, 6.95GHz BW, 30GHz UGB, and 55o phase margin. The circuit consumes 1.4mW power from a 1.8V power supply. Simulation results of the proposed circuit are comparable and better than the reported wideband designs in the literature. Realization of our proposed circuit would add value to the area of wideband amplifier design.

A UWB LNA with cascade of CCG and CS stage with improvement in gain and noise in 90-nm technology

A UWB LNA with cascade of CCG and CS stage with improvement in gain and noise in 90-nm technology

A Threshold-Based Bioluminescence Detector With a CMOS-Integrated Photodiode Array in 65 nm for a Multi-Diagnostic Ingestible Capsule

This article presents a highly miniaturized ingestible electronic capsule for biochemical detection via onboard genetically engineered biosensor bacteria. The core integrated circuit (IC) is a threshold-based bioluminescence detector with a CMOS-integrated photodiode array in a 65-nm technology that utilizes a dual-duty-cycling front end to achieve low power consumption. The implemented IC achieved 59-nW active power consumption, 25-fA/count resolution, and a 59-fA minimum detectable signal (MDS) using a calibrated optical source. The IC was then integrated with other system components into a battery-powered wireless ingestible capsule measuring just 6.5 mm thick <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 12 mm diameter. We demonstrated successful detection of low-intensity bioluminescent signals from bioengineered bacterial sensors when exposed to the intestinal inflammation biomarker tetrathionate in vitro. Together, the IC and mm-scale smart pill systems demonstrate high sensitivity with low-power multiplexed measurement capability suitable for noninvasive disease diagnosis and monitoring in the gastrointestinal (GI) tract.

An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache

This article presents an energy-efficient accelerating system-on-chip (SoC) for super-resolution (SR) image reconstruction on a mobile platform. With the rise of contactless communication and streaming services, the need for SR is growing. As one of the most basic low-level image processing algorithms, SR can reconstruct high-quality images from low-quality images which are noisy, compressed, or with damaged pixels. However, a massive amount of computation and considerable precision of pixel data pose challenges for acceleration in a resource and bandwidth constrained platform. SR has high energy consumption and long latency. While previous neural processing units (NPUs) reduced the precision to increase the efficiency and accelerate convolutional neural network (CNN) computation, few of them concentrated on both the output image quality and the performance of the entire system. The proposed SR SoC restores the high-quality image using a precision-optimized SR algorithm on an energy-efficient accelerating architecture and cache subsystem. It contributes three algorithm-hardware co-optimized features: 1) heterogeneous accelerating architecture (HAA) with only 8-bit floating-point (FP)-and-fixed-point (FXP) hybrid-precision for SR task; 2) tile-based hierarchical cache (THC) subsystem for the low energy and small footprint cost layer fusion; and 3) heterogeneous L1 data lifetime-aware optimized cache (DLOC) for the energy-efficient on-chip memory access. The prototype of SR SoC is fabricated in 65-nm technology and occupies a 10.0-mm2 die area. The proposed SR SoC can maintain the high reconstruction quality while consuming only 19% of the energy of an FXP16 system with homogeneous NPU. As a result, the SR SoC presents <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6\times $ </tex-math></inline-formula> higher energy efficiency than the previous SR targeting NPU and achieves 107-frame-per-second (fps) framerates running <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> SR image generation to full high definition (FHD) scale at only 0.92-mJ/frame energy consumption.

An All-1.8-V-Switch Hybrid Buck–Boost Converter for Li-Battery-Operated PMICs Achieving 95.63% Peak Efficiency Using a 288-m DCR Inductor

In this article, a hybrid step-up/down converter is presented with improved efficiency, smaller form factor, and enhanced reliability for Li-ion-battery-operated power management integrated circuits. Utilizing a hybrid structure with one inductor and two flying capacitors, the dual-path buck–boost (DPBB) converter reduces the average inductor current, switch currents, and the required blocking voltage for the power switches. To support a mid-3-V output from a Li-ion battery, the converter can be realized using 1.8-V rated devices, solely. In addition, the DPBB facilitates a continuous input and output current delivery, thus improving the reliability of the converter significantly. Besides, leveraging the Li-ion battery charge profile, the topology provides an optimal performance during downconversion, in which the converter operates for most of its usage time. With reduced inductor current and smaller voltage rated switches, a more compact inductor with a large dc resistance (DCR) can be used to maintain similar efficiency, which, in turn, helps reduce the converter board space and associated manufacturing cost. Fabricated in a 180-nm BCD technology, the prototype achieves a peak efficiency of 95.63% even for a large 288-m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> inductor DCR with an output ripple below 20 mV for a load current up to 700 mA.

Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology

This is the first work that employs the body biasing feature, available in fully depleted silicon on insulator (FDSOI) technology nodes, to build CMOS-compatible compact majority (MAJ) and minority (MIN) logic gates. Compared to their CMOS counterpart, our novel MAJ/MIN gates exhibit considerably fewer transistors, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2.3} \times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2} \times $ </tex-math></inline-formula> , respectively. The use of MAJ/MIN gates for logic synthesis has been widely investigated in the literature since any function can be realized using only these two gates. Nevertheless, the use of MAJ/MIN gates to synthesize circuits remained very limited because such gates are area hungry when implemented using conventional standard cells. Therefore, state-of-the-art research in the last decade has extensively focused on exploring beyond-CMOS technologies to build alternative MAJ/MIN gates. However, such emerging technologies are still immature and suffering considerably from variability. On the other hand, our novel FDSOI-based MAJ/MIN gates are based on mature CMOS commercial technologies. Our analysis of the proposed gates has been conducted using accurate SPICE simulations with an industry-compact transistor model, BSIM-IMG, calibrated for an industrial 14nm FDSOI technology. Using our developed MAJ/ MIN synthesis and error injection framework called MAJinBoo, we demonstrate that MAJ/MIN-based circuits exhibit an outstanding resiliency against errors due to the inherent voting-based computing. This encourages the employment of our MAJ/MIN gates in safety-critical applications where reliability is a prime concern. Our MAJinBoo framework is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/Brunno815/MAJinBoo</uri> .

DC-Coupled Ultra Broadband Differential to Single-Ended Active Balun in 130-nm SiGe BiCMOS Technology

The dc-coupled (DCC) broadband operation is a fundamental requirement in many applications, especially in optical communication systems. However, circuits allowing differential to single-ended conversion in a DCC fashion are very rare to be found in the literature. In this letter, a novel differential to single-ended ultrabroadband DCC balun in a 130-nm SiGe BiCMOS technology featuring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{t}/f_{\max }$ </tex-math></inline-formula> of 300/500 GHz is presented. A circuit analysis and a performance comparison between the proposed balun and two other configurations which are commonly used to convert a differential signal to a single-ended one is carried out. The design of the mentioned balun is described focusing on the trade-offs between gain, bandwidth (BW) and linearity. Measurement results show how the presented topology can achieve a low-frequency power gain of −7 dB and a 1 dB BW of 80 GHz, along with a total harmonic distortion (THD) of 7%.

Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region

This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking system over a wide voltage region. This paper focuses on the MEP characteristics that the energy loss is sufficiently small even though the voltage point changes near the MEP. For example, the energy loss is less than 5% even though the estimated MEP differs by a few tens of millivolts in comparison with the actual MEP. Therefore, the complexity for determining the MEP is relaxed by approximating complex operations such as the logarithmic or the exponential functions in the MEP tracking algorithm, which leads to hardware-/software-efficient implementation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1ms to 13µs by the proposed approximation. When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter. Measurement results of a 32-bit RISC-V processor fabricated in a 65-nm SOTB process technology show that the energy loss introduced by the proposed approximation is less than 2% in comparison with the MEP operation. Furthermore, we show that the MEP can be tracked within about 45 microseconds by the proposed MEP tracking system.

Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

HW/SW Codesign for Approximation-Aware Binary Neural Networks

Binary Neural Networks (BNNs) are rapidly gaining remarkable attention due to their superiority in shrinking the model size, which outstandingly mitigates the fundamental “memory wall” bottleneck that is attributed to the existing von-Neumann architectures. This work investigates how principles from approximate computing can be effectively employed to further optimize BNNs. It demonstrates that HW/SW codesign, in which BNNs are either proactively trained in the presence of approximation-induced errors (i.e. design-time optimization) and/or augmented with an appropriate error-mitigation scheme (i.e., run-time optimization), is a key to realize energy-efficient yet robust BNNs. We unveil, for the first time, that although the underlying HW of BNNs can be implemented using simple <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">XNOR</monospace> gates, the complexity of the required “Popcount” circuit super-linearly grows with the filter kernel size. This largely impacts the area footprint, inference time, energy, and hence it severely constricts the prospective efficiency gains from BNNs. To overcome this challenge, we replace the accurate full adders constructing the Popcount with Majority gates that approximately perform the required additions. Then, our carefully-crafted error-mitigation scheme along with activations tuning considerably minimizes the induced errors. Afterward, abstracted error probabilities are derived and employed during BNN training to obtain approximation-aware BNNs, that are inherently robust against the underlying HW approximation. Differently from the typical approaches, the proposed HW/SW codesign methodology has the merit of allowing a training of the approximate BNN without the need to modify the existing software frameworks (i.e., PyTorch). This is of great importance since existing tools rely on efficient built-in functions that can be difficult and/or inefficient to be modified. An FPGA-based SoC realizing both accurate and approximation-aware BNNs is developed for validating our proposed methodology. With merely a 4.7% loss in the inference accuracy, our HW/SW codesign leads to 64% and 80.2% savings in the area and energy, respectively, at the parity of the latency. Our results are obtained using commercial EDA tool flows employing a commercial 28nm FDSOI technology node.

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

Performance Evaluation of Different Topologies of SRAM and SRAM Memory Array Design at 180nm Technology

Memory circuits such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) form an integral part of system design and contribute significantly to system-level power consumption. Memory operating speeds and power dissipation have become important parameters due to the explosive growth of battery-operated appliances and the increased integration of circuits Hence SRAMs with different topologies are examined in terms of parameters like propagation delay, Static Noise Margin (SNM), corner analysis, and static power dissipation by simulating using versatile tool cadence virtuoso at 180nm technology. Besides, topological performance comparison, the SRAM memory array has also been illustrated from 2×2, 4×4 to 8×8, thereby verifying the read and write modes of operation of SRAM.

Optimized reverse converters with multibit soft error correction support at 7nm technology

Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively.

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.