3D Packaging Research Articles

Recent Developments in Low Temperature Wafer Level Metal Bonding for Heterogenous Integration

Abstract An overview of various low-temperature (<200°C) wafer bonding processes using metal interlayers is presented. Such processes are very attractive for novel applications in 3D heterogenous packaging as the allow for simultaneous formation of electrical interconnects, as well as hermetic encapsulation of various sensors and microelectromechanical systems-based devices. Metal wafer bonding is a generic category of processes consisting of various sub-categories, each one defined by the different principles governing the process. One can differentiate between eutectic wafer bonding (a eutectic alloy is formed as bonding layer during the process by liquid-solid interdiffusion), intermetallic wafer bonding (an intermetallic alloy is formed as bonding layer during the process by solid-liquid interdiffusion, a process known also as solid liquid intermetallic diffusion transient liquid phase, and metal thermo-compression wafer bonding. Different critical/gating parameters were investigated and their impact for generally reducing processing temperatures for the different metal bonding systems was studied.

Design and Architecture Definition for Advanced 3D Fan-Out Wafer-Level Packaging

Advanced 2.5D/3D wafer-level fan-out packaging technologies have been studied widely in literature and industry in recent years. Miniaturization, reduction in manufacturing costs, improvement in performance, and lower power consumption using packaging technologies drive increase in interconnect density and pitch scaling. Heterogeneous systems in package used in advanced packaging often include a combination of silicon, epoxy underfill or mold compounds, and organic or inorganic passivation or redistribution layers. This heterogeneity poses challenges with manufacturability, process selection, package architecture, and test vehicle design. The coefficient of thermal expansion mismatch, wafer warpage, and wafer yield are some of the critical process challenges. Delamination of silicon side wall or passivation to epoxy underfill or mold compound, joint fatigue are critical reliability challenges. This article explores various processes and reliability challenges with 3D wafer-level fan-out packaging and provides package design and architecture guidelines to overcome these failure modes. Stacked die-to-wafer test vehicles have been used for data collection. Different assembly materials, processes, and tooling have been evaluated to define comprehensive design rules.

Progress in Research on Co-Packaged Optics

In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a solution to meet the growing demand for data. Compared to typical optoelectronic connectivity technology, CPO presents distinct benefits in terms of bandwidth, size, weight, and power consumption. This study presents an overview of CPO, highlighting its fundamental principles, advantages, and distinctive features. Additionally, it examines the current research progress of two distinct approaches utilizing Vertical-Cavity Surface-Emitting Laser (VCSEL) and silicon photonics integration technology. Additionally, it provides a concise overview of the many application situations of CPO. Expanding on this, the analysis focuses on the CPO using 2D, 2.5D, and 3D packaging techniques. Lastly, taking into account the present technological environment, the scientific obstacles encountered by CPO are analyzed, and its future progress is predicted.

High-reliability Sn37Pb/Sn58Bi composite solder joints by solid-liquid low-temperature soldering

As the feature sizes of integrated circuits approach their physical limits, 3D packaging has emerged as a crucial technology for enhancing integration and extending Moore's Law. To meet the future requirements for low-temperature solder and interconnect processes in aerospace 3D packaging, this study combined Sn37Pb solder balls with Sn58Bi solder paste to prepare uniform composite solder joints under reflow conditions of 180°C for 10 minutes (CS-180–10) and 190°C for 1 minute (CS-190–1). The Bi atoms dissolved in the Pb phase strengthened the composite solder and made the crystal structure more ordered and predictable. The composite solder joints formed under both process conditions exhibited shear strengths higher than those of Sn37Pb solder joints prepared at 220°C for 1 minute, both before and after aging at 100°C. The fracture mode of the composite solder joints transitioned from ductile to mixed ductile-brittle with aging. Additionally, the composite solder demonstrated better creep resistance than SnPb solder at all tested strain rates in nanoindentation tests. Compared to CS-180–10, the lower heat input CS-190–1 featured finer Pb phases and Pb grains, better wettability, and better thermal stability. CS-190–1 showed only a 5.9 % decrease in shear strength after 42 days of aging at 100°C. This study offers a new solution for low-temperature, high-reliability interconnections in future aerospace integrated circuit 3D packaging.

Next Generation Heterogeneous 3D IC Chip Packaging

The demand for a faster and more efficient IC has been steadily increasing more than ever to accommodate the trend of Artificial Intelligence, Industry 4.0, Machine Learning, and Big Data. Traditionally, the semiconductor industry has kept up with demand of faster and more efficient IC by shrinking the size of transistor. As we approach a 1 nm transistor the technological challenge will be challenging to overcome as quantum tunneling becomes more pronounced and would decrease the reliability of the chip. To overcome this technological challenge, an advance packaging of 3D IC chip technology has been developed and delivered to market such as CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out). However, the aforementioned technology have their drawbacks with CoWoS uses interposer and TSV (through-silicon substrate via) which make it costly, time consuming, and wastes a lot of energy and InFO is limited in the number of layers it can accommodate for chiplets. Both of those technology are currently limited to 2 or 3 layer of IC and difficult to be modularize. In this study, we aim to develop a heterogeneous 3D IC package that can overcome the aforementioned problem which is modular, cost-effective, able to integrate chip from different manufacturers, and capable to stack more than 3 layers of ICs. This study has successfully completed the first stage of development by employing an advanced package consisting of Epoxy substrate with 200Å Ti/500Å Pt/1000Å Au metal interconnects, previously fabricated as a base for 3D stacking. Keywords : 3D IC Package, Advance Packaging, Modulable IC Packaging, Heterogeneous Integration Figure 1

Effect of different Ba/Sr ratios on the properties of borosilicate glasses for application in 3D packaging

Borosilicate glass is a promising material for 3D system integration technology due to its high integration and adjustable CTE (coefficient of thermal expansion). However, the structure and composition of borosilicate glasses result in a relatively high melting point and dielectric loss, which hinders the wide application of such glasses. In this study, we analyze the relationship between different Ba/Sr ratios and the structure and properties of the glass. We determine and further analyze the effect of mixed alkaline earth effect on the proportion of the Qn unit, [BO3], and [SiO4] in the glass structure, and consequently, its influence on the dielectric properties. Alkaline earth metals act as network-modifying ions to reconnect the interrupted network of the glass, stabilizing the glass structure and reducing the polarization loss of the glass. Raman analysis showed that the Raman spectrum shifted towards higher frequencies as the ratio of Al2O3/RO increased, with the Raman bands at 1300 cm−1-1500 cm−1 almost disappearing, while the Raman area at 730 cm−1-830 cm−1 increased. This indicated that the [BO3] units formed a ring structure in the glass, thereby enhancing the compactness of the glass network. The thermal expansion coefficient was 4.09 ppm K−1 when the Ba/Sr ratio was 1:1, and the dielectric constant and dielectric loss were 4.3 and 1.24 × 10−3, respectively. Overall, the dielectric properties and thermal expansion coefficients of the glass can be effectively reduced by doping with alkaline-earth metals, making the borosilicate glass more suitable for three-dimensional integrated system packaging.

Low-Temperature Bonding Materials and Insulation Materials for High-Density 3D Packaging

Low-Temperature Bonding Materials and Insulation Materials for High-Density 3D Packaging

Compact low-loss diplexer with stacked 2D and 3D structures using 3D glass-based advanced packaging technology

A compact low loss wideband diplexer is introduced by using stacked 2D and 3D structures through 3D advanced packaging and through glass vias (TGV). An inductor is designed by using stacked 2D and 3D structures to reduce the coupling effect between adjacent 2D inductors located in the same layer. It can greatly improve the Q factor yet minimize the chip size. This low loss, small size diplexer is developed by virtue of a modified topology and the proposed stacked 2D and 3D structures. The designed diplexer with a compact size of 1.6 mm × 0.8 mm × 0.25 mm is fabricated using 3D glass-based advanced packaging technology and measured by on-wafer probing. The measured results indicate that it achieves an insertion loss less than 0.8 dB and 0.9 dB and an isolation better than 20 dB and 17.5 dB in the bands of 0.699 GHz-0.960 GHz and 1.71 GHz-2.69 GHz, respectively. In comparison with the previously reported designs, the proposed diplexer shows the superior advantages of smaller size and lower insertion loss.

Effect of bonding time on reliability of Cu/Sn-9Zn-30Cu/Cu solder joints for 3D packaging

Effect of bonding time on reliability of Cu/Sn-9Zn-30Cu/Cu solder joints for 3D packaging

Integrated manifold microchannels and near-junction cooling for enhanced thermal management in 3D heterogeneous packaging technology

The rapid advancement in electronic chip technology is driving the evolution of highly integrated and high-power configurations, which in turn imposes greater demands on thermal management. This study presents a novel approach to address the thermal management challenges associated with high-density integrated chips. By incorporating the near-junction cooling method into silicon-based chips, the thermal resistance during heat conduction is effectively reduced. To further enhance heat dissipation efficiency, we integrate manifold microchannels and near-junction cooling into an aluminum nitride ceramic substrate, creating a heterogeneous three-dimensional integrated chip. To verify the effectiveness of our approach, a thermal test chip and an aluminum nitride substrate with a manifold structure are meticulously prepared and packaged for experimental testing. Remarkably, the experimental results demonstrate that the heterogeneous integrated chip, featuring manifold microchannels, achieves an impressive heat dissipation capacity of 700 W/cm2 under normal operating temperature conditions. Additionally, sensitivity analysis and multi-objective optimization approach were employed, utilizing the Response Surface-Genetic Algorithm П(NSGAП), to optimize the manifold microchannels in the heterogeneous integrated chip. The optimization process yields significant improvements, reducing the total thermal resistance of the chip by 13.6 % and the maximum pressure drop by 68.5 %. These findings provide valuable theoretical insights and guidance for the thermal design of high heat flux integrated chips, and contribute to advance the design and development of high-performance integrated circuit systems.

Assessment of the Relationship between Antero-Posterior Dental Malocclusions, Body Posture Abnormalities and Selected Static Foot Parameters in Adults.

Objectives: This study aimed to find if a relationship exists between antero-posterior malocclusions and the level of musculoskeletal disorders in adults, including body posture and static foot analysis. Methods: In all, 420 participants were recruited through convenience sampling (Kraków University students and patients of a local dentist's practice). Following general medical interviews, dental examinations and consideration of inclusion and exclusion criteria, 90 healthy volunteers (ages 19-35) were enrolled and assigned to three groups (n = 30) based on occlusion type (Angle's molar Class I, II or III). The research procedure involved occlusion and temporomandibular disorder assessment conducted by a dental specialist. Comprehensive morphological measurements of body asymmetry were performed using the Videography 2D package and FreeSTEP software, which calculated the parameters determined from anterior, posterior and lateral projection photos. Foot loading distribution was analyzed using the FreeMED baropodometric platform. Results: Significant differences were demonstrated in the positioning of the head, cervical and lumbar spine in the sagittal plane among individuals with the analyzed occlusal classes (p < 0.05). Individuals with Angle's Class II exhibited significantly greater forward head positions and greater depths of cervical and lumbar lordosis compared with individuals with Class III or Class I. Those with overbites had higher forefoot loading. The Class III individuals exhibited greater L-R displacement, indicating a larger angle of displacement of the centers of the right and left feet relative to the lower edge of the measurement platform, suggesting pelvic rotation. Conclusions: An inclination for concurrent occurrences of malocclusions and posture deviations in the sagittal plane was observed. An interdisciplinary approach involving dentistry and physiotherapy specialists which utilizes tools for comprehensive posture assessment is crucial for diagnosing and treating such conditions.

Spray mist-assisted drilling of through silicon vias (TSV) using nanosecond laser: Influence of CNT nanofluid

Through Silicon Vias (TSV) are crucial in semiconductor technology for vertically connecting multiple stacks in 3D packaging. High aspect ratio, smooth and slightly tapered TSVs enhance layout efficiency and void-free filling. Being contact-less and dry-etching process, laser machining is a promising technique to fabricate TSVs. A percussion laser drilling approach was used to fabricate TSVs on a 500 μm thick silicon wafer with a 1064 nm ns laser. Four environments such as air, compressed air jet, water mist, carbon nanotube (CNT) fluid mist were employed to assess laser machining effects on TSV performance in terms of entrance and exit diameters, recast layer, side wall damage, and taper angle. Optimized process parameters (laser pulse energy and pulse number) were derived from an ANN prediction model. Laser drilling under CNT mist produced relatively circular (entrance diameter), straight, and clean TSVs. Reduced debris redeposition was observed under air jet, water mist, and CNT mist compared to air. Minimal sidewall damage occurred under water mist and CNT mist as compared to those machined in air and air jet. CNT mist yielded TSVs with less recast layer (∼7 μm), taper angle (∼1.05 deg.), and heat affected zone (HAZ) thickness (∼50 μm). Enhanced machining quality may be attributed to increased thermal conductivity of CNT nanofluid and pressurized mist flow rate, improving cooling and debris removal. Furthermore, a detailed investigation of TSV using SEM was performed and the findings were compared to those of other research groups.

An ultra-deep TSV technique enabled by the dual catalysis-based electroless plating of combined barrier and seed layers

Silicon interposers embedded with ultra-deep through-silicon vias (TSVs) are in great demand for the heterogeneous integration and packaging of opto-electronic chiplets and microelectromechanical systems (MEMS) devices. Considering the cost-effective and reliable manufacturing of ultra-deep TSVs, the formation of continuous barrier and seed layers remains a crucial challenge to solve. Herein, we present a novel dual catalysis-based electroless plating (ELP) technique by tailoring polyimide (PI) liner surfaces to fabricate dense combined Ni barrier/seed layers in ultra-deep TSVs. In additional to the conventional acid catalysis procedure, a prior catalytic step in an alkaline environment is proposed to hydrolyze the PI surface into a polyamide acid (PAA) interfacial layer, resulting in additional catalysts and the formation of a dense Ni layer that can function as both a barrier layer and a seed layer, particularly at the bottom of the deep TSV. TSVs with depths larger than 500 μm and no voids are successfully fabricated in this study. The fabrication process involves low costs and temperatures. For a fabricated 530-μm-deep TSV with a diameter of 70 μm, the measured depletion capacitance and leakage current are approximately 1.3 pF and 1.7 pA at 20 V, respectively, indicating good electrical properties. The proposed fabrication strategy can provide a cost-effective and feasible solution to the challenge of manufacturing ultra-deep TSVs for modern 3D heterogeneous integration and packaging applications.

Simulation based comparative analysis of electric field stress on insulated cross-arm

Insulated cross-arms for overhead transmission lines have become increasingly common in the past decade. The 3D finite element analysis (FEA) of the electric field distribution in insulated cross-arms is particularly intriguing due to the differences from conventional glass or ceramic insulators. The complex geometry of composite cross-arms, which feature four separate insulator strings and varying shed profiles, poses a challenge in modelling them using 3D FEA packages. The findings indicate that insulated cross-arms can operate within suitable parameters for traditional composite insulators. This paper presents and analyses the electric field distribution around an insulated cross-arm, which aims to replace existing high-voltage insulators and the steel cross-arms of transmission towers. The design of grading devices plays a crucial role in ensuring the safety of these structures. The use of grading ring devices at both ends of the insulator has proven effective in relieving stress on the insulator string under normal and abnormal conditions, enabling the insulated cross-arm to function effectively with conventional composite insulators. Significant reductions in electric field strength were observed, amounting to approximately 35.93 % inside the core, 31.14 % on the core surface, 35.64 % through the shed, and 16.67 % above the shed for compression members. For tension members, reductions from the low-voltage end to both ends were around 33.82 % inside the core, 38.55 % on the core surface, and 17.48 % through the shed. However, an 8.43 % increase was observed above the shed, indicating a deviation from the decreasing trend observed in other areas. These research findings provide valuable insights for designing and managing high-voltage systems, ensuring effective insulation and enhanced safety. It benefits electrical utilities and transmission line manufacturers by improving reliability and safety for overhead transmission lines.

Review on Power Cycling Reliability of SiC Power Device

The rising demand for increased integration and higher power outputs poses a hidden risk to the long-term reliable operation of third-generation semiconductors. Thus, the power cycling test (PCT) is widely regarded as the utmost critical test for assessing the packaging reliability of power devices. In this work, low-thermal-resistance packaging design structures of SiC devices are introduced, encompassing planar packaging with dual heat dissipation, press-pack packaging, three-dimensional (3D) packaging, and hybrid packaging. PCT methods and their control strategies are summarized and discussed. Direct-current PCT is the focus of this review. The failure mechanisms of SiC devices under PCT are pointed out. The electrical and temperature-sensitive parameters adopted to monitor the aging of SiC devices are organized. The existing international standards for PCT are evaluated. Due to the lack of authoritative statements for SiC devices, it is difficult to achieve comparison research results without consistent preconditions. Furthermore, the lifetimes of the various packaging designs of the tested SiC devices under PCTs are statistically analyzed. Additionally, problems related to parameter monitoring and test equipment are also summarized. This review explores the broader landscape by delving into the current challenges and main trends in PCTs for SiC devices.

The effect of boron anomaly on the dielectric properties and thermal expansion of barium borosilicate glasses for 3D packaging systems

Barium borosilicate (BBS) glass is a potential three-dimensional system packaging and sensor cover material. In this study, we prepared glass samples with different SiO2/B2O3 ratios based on the revised model of Dell and Bray and discussed the effect of boron anomaly on dielectric and thermal properties through Raman spectroscopy. The results indicate that the [BO4] tetrahedrons are beneficial in reducing the dielectric constant and dielectric loss to a certain extent, while the improvement in the coefficient of thermal expansion (CTE) is attributed to the depolymerization of the glass network by the [BO3] triangles. After the disappearance of the boron anomaly, a certain amount of dielectric performance is sacrificed in exchange for an increase in the CTE. When the substitution rate of B2O3 for SiO2 reaches 15.12 mol%, the CTE of the sample increases to 8.43 × 10−6/°C, in addition, the dielectric constant and dielectric loss decrease to 4.90 and 0.0071 (@1 GHz), respectively. In summary, this work provides a suitable method for preparing glass with a high coefficient of expansion and low dielectric loss to address the thermal mismatch effect of different materials in electronic packaging systems.

Predictive modeling of shallow tunnel behavior: Leveraging machine learning for maximum convergence displacement estimation

Accurate prediction of maximum convergence in unsupported, shallow tunnel construction is crucial for optimizing the lining and ensuring tunnel safety. Machine learning (ML) algorithms, especially through boosting techniques, enable effective solution of complex engineering problems and demonstrate their capabilities in problem solving and optimization. In this study, the FLAC 3D package was used to create a robust and validated database of 954 datasets. Five tree-based ML algorithms, including extreme gradient boosting (XGBoost), adaptive boosting (AdaBoost), gradient boosting machine (GBM), histogram-based gradient boosting (HGB) and categorical boosting (CatBoost), were used to predict the maximum convergence displacement for unsupported shallow tunnels. For the test dataset, XGBoost outperformed the other models with an excellent coefficient of determination of 0.9633, a minimum mean absolute error of 0.0021 and a low root mean squared error of 0.00725. HGB followed closely behind, and GBM and CatBoost showed strong performances, while Adaboost was less effective. The superior performance of XGBoost highlights its effectiveness in predicting maximum convergence in shallow tunnels. An in-depth sensitivity analysis within the XGBoost model showed the significant influence of soil elastic modulus on the maximum convergence displacement in unsupported tunnels. The remarkable results achieved by the XGBoost algorithm on our complex tunnel convergence predictions illustrate the profound ability of ML to tackle complicated geotechnical challenges. This interdisciplinary collaboration demonstrates the potential of advanced algorithms to improve safety and efficiency in construction, underlining the crucial role of technology in tackling complex problems and establishing a new paradigm for innovation in the field.

Thermal and compositional fields to maneuver Cu6Sn5 intermetallic growth on (111) nanotwinned copper substrate

The microstructure of the Cu6Sn5 phase plays a pivotal role in the functionality of microbumps utilized in 3D packaging. In this study, we present an experimental methodology aimed at maneuvering the orientation and morphology of Cu6Sn5 grains formed on (111) nanotwinned Cu substrate, achieved through variations in reflow temperatures (260∘C and 300∘C) and initial Cu proportion in solder (ranging from 0 to 3.0 wt%). At 300∘C and lower initial Cu concentrations (0 and 0.7 wt%), irregularly arranged roof-type Cu6Sn5 grains exhibiting a pronounced {21¯1¯0} texture were observed. Conversely, typical scallop-type Cu6Sn5 grains displaying a specific preferential {21¯1¯3} texture were identified at this temperature for Cu concentrations of 1.5 and 3.0 wt% At 260∘C, the scallop-type morphology was solely present at all Cu composition variants. The differing rates of solute controlled intermetallic phase clustering mechanism at altered solubility limits and magnitudes of thermodynamic driving force for different temperatures, can decide the relative loss of interface coherency and subsequently change the preferred orientation direction of evolving interfacial structures. Our findings demonstrate that the precise control over soldering temperature, solder Cu composition, and the microstructure of Cu UBM can enable the attainment of Cu6Sn5 microstructure with a designated orientation and morphology.

Materials and manufacturing technology for high reliability rigid-flex multilayer PCB for space 3D-electronics packaging

Rigid-flex Multilayer PCB Technology enables the elimination of several connectors and bulky harness for interconnecting functional electronic systems. This minimizes packaging complexity and reduces performance degradation at high frequencies with an added advantage of reduced weight and volume in high-reliability space electronic packages. Here, only thermo-mechanically stable adhesiveless all polyimide flexible laminate cores and no-flow glass-polyimide prepregs are employed. To overcome the manufacturing issues like registration, coverlay protrusion into the rigid portions, and residual copper deposition at the intersections of flexible and rigid portions; a novel manufacturing process technology is proposed here. The technology has been successfully devised after choosing the most appropriate flexible, rigid, and low-flow prepreg materials. Herein, for the realization of rigid-flex multilayer PCB technology with 2-layers of flex and 8-layers of rigid to meet the functional requirements of the board is presented. The critical registration issues associated with the dissimilar rigid and flexible substrates are successfully addressed to achieve best-fit registration and obtain minimum annular rings of 50 μm in all the inner layers for high reliability. Experimental results manifest that incorporating rigid-flex multilayer PCB technology dramatically reduces weight (>30%) and volume (∼40%) to high-reliability space electronics 3D packaging for static and dynamic applications.

Superconducting quantum memory with a suspended coaxial resonator

A promising way to store quantum information is by encoding it in the bosonic excitations of microwave resonators. This provides for long coherence times, low dephasing rates, as well as a hardware-efficient approach to quantum error correction. There are two main methods used to make superconducting microwave resonators: by traditionally machining them out of bulk material and by lithographically fabricating them on a chip in thin film. 3D resonators have few loss channels and larger mode volumes, and therefore smaller participations in the lossy parts, but it can be challenging to achieve high material quality. On-chip resonators can use low-loss thin films, but they confine the field more tightly, resulting in higher participations and additional loss channels from the dielectric substrate. In this work, we present a design in which a dielectric scaffold supports a thin-film conductor within a 3D package, thus combining the low surface participations of bulk-machined cavities with high quality and control over materials of thin-film circuits. By incorporating a separate chip containing a transmon qubit, we realize a quantum memory and measure single-photon lifetimes in excess of a millisecond. This hybrid 3D architecture has several advantages for scaling as it relaxes the importance of the package and permits modular construction with separately replaceable qubit and resonator devices.