3D Integrated Circuit Packaging Research Articles

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

Interfacial reaction between novel high entropy alloy SnPbInBiSb and Cu substrate

With the rapid development of electronic packaging technology, the high reliability of 3D integrated circuit packaging calls for new functional solder. In this study, a novel high entropy alloy SnPbInBiSb with a low melting point of 112.8 °C was fabricated and investigated. The low melting point and excellent wettability of SnPbInBiSb alloy prove its great potential as a new kind of solder applied in low-temperature electronic packaging. Moreover, the interfacial reaction of the Cu/SnPbInBiSb/Cu solder joint was studied. The sluggish diffusion effect and lattice distortion effect of SnPbInBiSb distinctly restrained the interdiffusion between alloying elements and Cu, thus hindering the growth of intermetallic compounds along the SnPbInBiSb/Cu interface.

Interfacial Reactions of Ag and Ag-4Pd Stud Bumps with Sn-3Ag-0.5Cu Solder for Flip Chip Packaging

The wettability and growth of intermetallic compounds (IMCs) of stud bump materials Ag, Ag-4Pd, Cu, and Au with Sn-3Ag-0.5Cu (SAC305) solder have been investigated. Stud bumps produced using wire bonding techniques are widely employed in flip chip assembly, especially in 3D integrated circuit packaging. The material of stud bumps is a key factor in the reliability of the bonds. The wettability of IMCs as studied in this study decreased in the order Au > Ag ≈ Ag-4Pd > Cu, indicating that Ag and Ag-alloy bumps were only slightly inferior to those of Au but superior to those of Cu. Moreover, the morphologies and growth behaviors of the IMCs were evaluated by aging at 100°C to 200°C for 100 h to 1000 h. Without the gold embrittlement effect found in Au or the Kirkendall void issue of Cu, IMCs contained mainly Ag3Sn at the interface after long-term aging tests, and thickened IMCs with Ag3Sn and PdSn4 were observed in the case of Ag-4Pd after prolonged aging for 1000 h at 200°C. The growth kinetics of the IMCs in Ag and Ag-4Pd stud bumps with SAC305 solder followed the Arrhenius equation, with activation energies of 56.45 kJ/mol and 57.37 kJ/mol, respectively. The formation mechanisms of the IMCs in Ag and Ag-4Pd stud bumps were found to be diffusion controlled. The results indicated that Ag and Ag-4Pd are better than Au and Cu for application as stud bump materials.

Optimization of 3D IC stacking chip on molded encapsulation process: a response surface methodology approach

The stress concentration and deformation of the 3D stacked IC structures can be minimized with an optimal design of the integrated circuit (IC) using a response surface methodology. The geometrical and process parameters (i.e., A = inlet pressure, B = solder bump standoff height, C = chip thickness, and D = aspect ratio) were optimized via a central composite design (CCD) for the molded encapsulation process. The fluid/structure interaction (FSI) aspects were considered in the optimization of the molded encapsulation process. The separate effects of the independent variables and their interactions were studied. The calculated empirical models were carried out and well validated with the simulation results. The optimum geometrical and process parameters of the 3D stacked IC package with perimeter solder bump arrangement were characterized as follows: inlet condition of 3.65 MPa, 150 μm of solder bump standoff height, 250 μm of chip thickness, and 2.1 of aspect ratio. The outcomes herein may significantly contribute to the advancement of microelectronic industries.

Technology for 3D System Integration for Flexible Wireless Biomedical Applications.

This paper presents a new 3D bottom-up packing technology for integrating a chip, an induction coil, and interconnections for flexible wireless biomedical applications. Parylene was used as a flexible substrate for the bottom-up embedding of the chip, insulation layer, interconnection, and inductors to form a flexible wireless biomedical microsystem. The system can be implanted on or inside the human body. A 50-μm gold foil deposited through laser micromachining by using a picosecond laser was used as an inductor to yield a higher quality factor than that yielded by thickness-increasing methods such as the fold-and-bond method or thick-metal electroplating method at the operation frequency of 1 MHz. For system integration, parylene was used as a flexible substrate, and the contact pads and connections between the coil and chip were generated using gold deposition. The advantage of the proposed process can integrate the chip and coil vertically to generate a single biocompatible system in order to reduce required area. The proposed system entails the use of 3D integrated circuit packaging concepts to integrate the chip and coil. The results validated the feasibility of this technology.

Analytical and finite element methodology modeling of the thermal management of 3D IC with through silicon via

Purpose This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs). Design/methodology/approach This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package. Findings This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package. Research limitations/implications Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed. Practical implications The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board. Social implications In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model. Originality/value The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

Phase Change Material for Thermal Management in 3D Integrated Circuits Packaging

Effective thermal control and management in three-dimensional electronic packaging are desirable to ensure the heat generated in integrated circuits can be dissipated. Conventional base materials in electronics from substrate to protective layers, due to low coefficient of thermal conductivity, cannot help to cool down the circuits, while such elevated temperature could highly impact the performance of the chips. In this study, phase change material (PCM) is selected for potential applications in thermal management of electronic packaging due to its isothermal nature and high thermal storage capability. PCM based composite is developed through the impregnation technology using highly porous expanded graphite. Heat transfer test results reveal that the PCM based composite displays superior heat storage capacity, while maintaining the favorable feature of thermal and chemical stabilization for electronic applications. Toward the end, the concept of implementation of PCM based composite is proposed in thermal control of 3D integrated circuits. It is expected the proposed composite will improve heat dissipation, and ultimately enhance the performance of the chips.

Determination of Initial Crack Strength of Silicon Die Using Acoustic Emission Technique

The current market demand for high-efficiency, high-performance, small-sized electronic products has focused attention on the use of three-dimensional (3D) integrated circuits (IC) in the design of electronic packaging. Silicon wafers can be ground and polished to reduce their thickness and increase the chip stacking density. However, microcracks can result from the thinning and stacking process or during use of an electronic device over time; therefore, estimation of the cracking strength is an important issue in 3D IC packaging. This research combined the ball breaker test (BBT) with an acoustic emission (AE) system to measure the allowable force on a silicon die. To estimate the initial crack strength of a silicon die, the BBT was combined with finite-element (FE) analysis. The AE system can detect the initial crack and the subsequent bulk failure of the silicon die individually, thus avoiding overestimation of the die strength. In addition, the results of the modified ball breaker test showed that edge chipping did not affect the silicon die strength. However, the failure force and silicon die strength were reduced as the surface roughness of the test specimen increased. Thus, surface roughness must be controlled in the BBT to prevent underestimation of the silicon die strength.

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging

Three-dimensional (3-D) integration and packaging with through silicon via (TSV) is an emerging trend for overcoming the limitation of integration scale in Micro-electro-mechanical systems (MEMS) packaging. It is helpful for the realization of high density and reliability of micro-devices and sensors. The technology of fabricating copper (Cu) TSVs by electroplating is applied to provide communication links in vertical direction. The fabrication of defect-free and time-saving TSV is our destination. In this paper, the Cu deposition mechanism was analyzed and the process was expressed by a series of electrochemical equations. Finite element models were built to simulate two different kinds of Cu electroplating processes in through-hole via. 100mm diameter and 370μm thick polished silicon wafers were chosen in experiments. Under the guidance of the simulation results, defect-free Cu TSVs were obtained by using double-sided and bottom-up electroplating methods respectively. Electrolyte additives affected the Cu deposition velocity and direction to a certain extent. Comparing the two electroplating methods, we found that double-sided electroplating is economical and time-saving. While, bottom-up electroplating has the capability in filling the through-holes whose aspect ratio are greater than 10:1. It only took about 2.5h and 3.5h to obtain the intact Cu TSVs by using double-sided and bottom-up electroplating methods respectively. Finally, Cu TSVs were successfully applied to the Wafer Level Packaging (WLP) Pirani vacuum gauges for the vacuum packaging of MEMS. The vertical leakage rate of bonding samples ranged from 1.0E-9Pam3/s to 4.5E-8Pam3/s, which were measured by helium leak detector.

Fluid–structure interaction analysis on the effect of chip stacking in a 3D integrated circuit package with through-silicon vias during plastic encapsulation

This paper presents the effect of chip stacking in a 3D integrated circuit package during plastic encapsulation. An experiment was conducted on four stacked chips with bumps in a perimeter array. The flow front advancement and chip displacement in the experiment were validated by using FLUENT 6.3 and ABAQUS 6.9, respectively. A total of four models, which consist of two, three, four, and five stacked chips with through-silicon vias, were studied numerically. A simultaneous or direct solution procedure was employed to solve the variables of the fluid/structural domain. This approach provides better visualization of the actual plastic encapsulation process by considering the fluid–structure interaction phenomenon during the process. A constant ratio of inlet and outlet gate heights was applied to create a more uniform flow front advancement among the models. Results indicate that the highest displacement occurred in Model 4, which contains the most stacked chips. The highest von Mises stress was also detected in Model 4. Therefore, unfavorable deformation is anticipated when more stacked chips are employed. The experimental and numerical studies provide useful information in understanding the fluid flow of epoxy resin and subsequent structural deformation under the effect of chip stacking.

Numerical Modeling and Analysis of Microbump Pitch Effect in 3D IC Package with TSV During Molded Underfill (MUF)

In this paper, the microbump pitch effect in molded underfill (MUF) is analyzed in the 3D integrated circuit (IC) package with a through-silicon via by numerical modeling. The current trend of decreasing the microbump pitch could make the MUF process more difficult. However, no detailed study on the particular area, particularly on the MUF process, has been conducted so far. Therefore, this paper could be a good reference by providing detailed information on the process. In our analysis, FLUENT 6.3.26 is used to predict the MUF flow front advancement under the effect of a different microbump pitch. The strong ability of FLUENT to predict flow front advancement was validated by the experimental results in the literature. Based on the analysis, the effect of the microbump pitch has significant implications on the filling rate, velocity profile, epoxy molding compound conversion rate, pressure distribution, and air void entrapment level. From the numerical analysis, a smaller microbump pitch is inferior in terms of the filling rate and air void entrapment level. The data and the analysis provide fundamental knowledge in understanding the effect of the microbump pitch on the MUF process.

Precipitation of large Ag3Sn intermetallic compounds in SnAg2.5 microbumps after multiple reflows in 3D-IC packaging

Microbumps have been adopted as interconnects between Si chips in 3D integrated-circuit packaging. The solder volume of a microbump decreases dramatically due to fine-pitch requirement and it is approximately two orders smaller in magnitude than that of a traditional flip-chip solder joint. The metallurgical reactions in the microbumps may behave quite differently to those in flip-ship bumps. Liquid-state metallurgical reactions were examined in SnAg2.5 microbumps with Ni metallization. The results indicate that large particles of Ag3Sn intermetallic compounds (IMCs) precipitate after a 10-min reflow on microbumps with 4.0-μm-thick solder, which does not occur with flip-chip solder bumps. It is proposed that the Ag concentration in the remaining solder may increase as Sn reacts with Ni. The increase in the Ag concentration is mainly responsible for the occurrence of the large Ag3Sn precipitates. The formation of these Ag3Sn IMCs would be detrimental to the mechanical properties of the microbumps.

Approaches to electronic miniaturization : H. M. B. Bird. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, 18 (2), 274 (June 1995).

Microbumps have been adopted as interconnects between Si chips in 3D integrated-circuit packaging. The solder volume of a microbump decreases dramatically due to fine-pitch requirement and it is approximately two orders smaller in magnitude than that of a traditional flip-chip solder joint. The metallurgical reactions in the microbumps may behave quite differently to those in flip-ship bumps. Liquid-state metallurgical reactions were examined in SnAg2.5 microbumps with Ni metallization. The results indicate that large particles of Ag3Sn intermetallic compounds (IMCs) precipitate after a 10-min reflow on microbumps with 4.0-μm-thick solder, which does not occur with flip-chip solder bumps. It is proposed that the Ag concentration in the remaining solder may increase as Sn reacts with Ni. The increase in the Ag concentration is mainly responsible for the occurrence of the large Ag3Sn precipitates. The formation of these Ag3Sn IMCs would be detrimental to the mechanical properties of the microbumps.