3D IC Packaging Research Articles

Microstructure of ternary Sn-Bi-xCu alloy on mechanical properties, current endurance and corrosion morphology via cycling corrosion test

Low melting temperature of Sn-58 wt.% Bi (SB) solders adding 0.5wt.% Cu (SB05C) and 1.7wt.% Cu (SB17C) concentrations were evaluated for the signal transmission in the 3D IC package. Microstructure combined with phase analysis and Pandat simulation were together with to explain the relationship among the mechanical property, electrical endurance and corrosion resistance. By Cu decoration, the presence Cu6Sn5 intermetallic compound (IMC) acts as heterogeneous nucleation sites to reduce surface free energy and generate fine Bi grain that resulted in higher hardness value. The power-law was used to explain the mechanism of interfacial IMC growth, both Cu6Sn5 and Cu3Sn formation were speculated to be volume diffusion control and surface reaction domination, respectively. The fracture morphology by shear testing indicates that earliest plastic deformation accompanied with brittle rupture were major factors due to the intergranular fracture and Cu6Sn5 compound induced bulk fracture. By cycling corrosion test (CCT), the lump shape of SnO2 by-product was found among solders at three cycling. After seven cycling, Sn phase has been completely corroded and Cu6Sn5 IMC began to be corroded forming circle shape of Cu2O but Bi phase still not be corroded among solders. In the electrical endurance, dense Cu6Sn5 dispersed in solder bulk and fine grain size were feasible to induce current crowding and joule heating, thus Cu deteriorated SB solders is easily failed.

Next Generation Heterogeneous 3D IC Chip Packaging

The demand for a faster and more efficient IC has been steadily increasing more than ever to accommodate the trend of Artificial Intelligence, Industry 4.0, Machine Learning, and Big Data. Traditionally, the semiconductor industry has kept up with demand of faster and more efficient IC by shrinking the size of transistor. As we approach a 1 nm transistor the technological challenge will be challenging to overcome as quantum tunneling becomes more pronounced and would decrease the reliability of the chip. To overcome this technological challenge, an advance packaging of 3D IC chip technology has been developed and delivered to market such as CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out). However, the aforementioned technology have their drawbacks with CoWoS uses interposer and TSV (through-silicon substrate via) which make it costly, time consuming, and wastes a lot of energy and InFO is limited in the number of layers it can accommodate for chiplets. Both of those technology are currently limited to 2 or 3 layer of IC and difficult to be modularize. In this study, we aim to develop a heterogeneous 3D IC package that can overcome the aforementioned problem which is modular, cost-effective, able to integrate chip from different manufacturers, and capable to stack more than 3 layers of ICs. This study has successfully completed the first stage of development by employing an advanced package consisting of Epoxy substrate with 200Å Ti/500Å Pt/1000Å Au metal interconnects, previously fabricated as a base for 3D stacking. Keywords : 3D IC Package, Advance Packaging, Modulable IC Packaging, Heterogeneous Integration Figure 1

A novel heat transfer characterization method for a thermal management scheme of 3D-IC chips

A novel surface-modified silicon-based thermal management technology has been proposed for 3D IC architecture in this study. 2 × 2 cm2 double sides polished silicon chips’ surface with micro-fin (MF) and micro-pin fin (MPF) structures have been achieved by applying silicon microfabrication technology of deep reactive ion etching, which is applicable to the interlayer of 3D IC packaging technology. By integrating a mini wind tunnel with Raman spectrometer, the transient thermal property measurement system is originally designed to evaluate the cooling capability of the surface-modified silicon interlayer. Finite Element Analysis was involved to confirm this view by taking fluid dynamics and heat transfer into account. The sample with 100 × 100 µm2 MPF structure expresses the appropriate exponential decay time constant τ (with unit of 1), which is 4.71 and 8.53 under cooling and heating measurement conditions, respectively. This also proved that the combination of Raman thermometry with forced gas flow could be a relevant measurement tool for transient thermal property.

Electromigration in three-dimensional integrated circuits

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging.

Challenges and prospects for advanced packaging

In the post-Moore era, advanced packaging is becoming more critical to meet the everlasting demands of electronic products with smaller size, more powerful performance and lower cost. In this paper, developments in advanced packaging have been discussed, such as 3D IC packaging, fan-out packaging, and chiplet packaging. Insights on the major advantages and challenges have also been briefly introduced. Our prospects about the solutions to some fundamental issues in sustainable development of advanced packaging have also been elucidated. The critical aspects and opportunities lie in standardization, co-design tools, new handling technologies, as well as multi-scale modeling and simulation.

Aerosol Jet Printed Interconnects for Millimeter-Wave Components

As millimeter wave RF device applications expand above traditional microwave frequency bands in the global communications, automotive and Mil-Aero markets, the need to limit interconnect signal losses related to parasitic elements has never been more important. As the frequency increases, device designers are facing numerous challenges, complications, and costs when fabricating interconnects with techniques such as copper pillar bumps, wire, ribbon or wedge bonding in 3DIC packaging. Printing conformal interconnects with Aerosol Jet® direct-write technology can offer package designers and RF engineers a new approach for optimizing interconnect transitions to active die, tailoring the loss characteristics to specific application requirements and eliminating the need to compensate for high signal transmission losses. Printed interconnects can be digitally designed into the package with a variety of metallic and dielectric materials. As these interconnects are conformally printed on the 3D surface of the package, the trace length can be minimized with zero loop height, reducing parasitic inductance to active die circuitry specifically for die on board, die in trench, or die on die with pads-up packaging configurations. In this work, Aerosol Jet® printed interconnects with silver nanoparticle inks are compared with the gold microstrip transmission lines as well as traditional gold bond wires, for performance up to 110 GHz. We will share examples showcasing that the printed interconnects can have similar RF transmission performance to microstrip, with significantly lower loss than bondwires especially at high frequencies. We will also discuss design effects for Aerosol Jet® printed RF interconnects up to 110 GHz based on a set of results for different line heights with a given line width printed with a silver ink.

Low-temperature Cu-to-Cu electrode bonding by sintering Cu core-Ag shell nanoparticle paste

Metal-to-metal bonding is critical in modern electronics technology such as 3D-IC packaging and automotive electronics. In this study, we applied Cu core-Ag shell nanoparticle paste (CANP) for bonding Cu electrodes and developed the CANP sintering conditions. The electrical conductivity of the CANP films sintered at 400 °C without pressure was 3.3–4.0 × 104 S/cm. Compact Cu-CANP-Cu joints could be fabricated by sintering the CANP at 350–400 °C under the bonding pressure of 1.0 or 1.7 MPa. Thermal conductivity and shear strength of the CANP joints increased with sintering temperature and bonding pressure, which is attributed to the enhanced interconnection of nanoparticles as shown by the scanning electron microscopy of the cross-section and the fractured surface of the CANP joints. The Cu-CANP-Cu joints had thermal conductivity up to 31.2 W/mK and shear strength up to 10.9 MPa when the CANP was sintered at 400 °C under 1.7 MPa. This work provides a pathway for a cost-effective and reliable sintering-bonding method for electronics packaging applications.

Low-Temperature Direct Bonding of 3D-IC Packages and Power IC Modules Using Ag Nanotwinned Thin Films

Ag has the lowest stacking fault energy of all metals, which allows twin formation to occur more easily. The (111)-preferred orientation Ag nanotwinned films is fabricated by either sputtering or evaporation method exhibit columnar Ag grains grown vertically on Si substrates. Ag nanotwinned films have a (111)-preferred orientation with a density about 98% and diffusivity that is 2 to 5 orders of magnitude higher than those of (100) and (110) surfaces. Low temperature direct bonding with (111)-oriented Ag nanotwins films is proposed to fulfil the requirements for wafer-on-wafer (WoW), chip-on-wafer (CoW), and chip-on-wafer-on-substrate (CoWoS) advanced 3D-IC packaging, with the process temperature drastically reduced to 100°C. Such an innovative bonding method also provides a promising solution for die attachment of Si chips with DBC-ceramic substrates for power module packaging.

(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling

3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1].In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated.

Interfacial Characterization of Low-Temperature Cu-to-Cu Direct Bonding with Chemical Mechanical Planarized Nanotwinned Cu Films.

Copper-to-copper (Cu-to-Cu) direct bonding is a promising approach to replace traditional solder joints in three-dimensional integrated circuits (3D ICs) packaging. It has been commonly conducted at a temperature over 300 °C, which is detrimental to integrated electronic devices. In this study, highly (111)-oriented nanotwinned (nt) Cu films were fabricated and polished using chemical mechanical planarization (CMP) and electropolishing. We successfully bonded and remained columnar nt-Cu microstructure at a low temperature of 150 °C thanks to the rapid diffusion of Cu on (111) surface. We employed a new microstructural method to characterize quantitatively the interfacial bonding quality using cross-sectional and plan-view microstructural analyses. We discovered that CMP nt-Cu bonding quality was greater than that of electropolished nt-Cu ones. The CMP nt-Cu films possessed extremely low surface roughness and were virtually free of pre-existing interface voids. Thus, the bonding time of such CMP nt-Cu films could be significantly shortened to 10 min. We expect that these findings may offer a pathway to reduce the thermal budget and manufacturing cost of the current 3D ICs packaging technology.

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

The approach of monolithic 3D IC (M3D) integration using monolithic inter-tier-vias (MIVs) as interconnect structures is considered. Although, M3D ICs show many benefits of heterogeneous integration without significant area overhead compared to 3D ICs, reliability and thermal issues become daunting challenges to be addressed. Hence, this study focuses on electromigration issues of current density, thermal stress, and structure deformation due to temperature loading. For the analysis Cu and carbon nanotube (CNT) filler materials were chosen in MIV structure. Our analysis reveals that CNT based MIV offers two-fold higher current density and 91% lesser thermal stress compared to Cu based MIVs. Furthermore, at different voltage values, the current density profiles are examined. For the comprehensive investigations of structure deformations, temperature gradient was allowed at the ends of the MIV structure. The results show less deformations in CNT compared to Cu, based on the stress induced among them. The failure time prediction shows higher mean time to failure value of CNT based MIV than Cu based MIV.

Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-Layered Stacked-Chip Packaging

Abstract To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is a three-dimensional integrated circuit (3D-IC) package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of microsolder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg microsolder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis (FEA) is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg microsolder joint can be achieved at 10 μm of each chip thickness, 230 μm and 5 μm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermomechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Reliability evaluation of ultra thin 3D-IC package under the coupling load effects of the manufacturing process and temperature cycling test

In the development of semiconductor packaging technology from planar to three-dimensional vertical integration, chip interconnection density has increased, and the distance of signal transmission has dropped to improve overall device performance. In this research, an architecture composed of through‑silicon via (TSV) and solder microbump (μbump) is utilized to assemble an ultra thin-type chip into a three-dimensional integrated circuit (3D-IC) package. To explore the influence of residual thermomechanical residual stress induced during the manufacture of the 3D-IC package on the subsequent reliability of the thermal cycling test (TCT), this study establishes a nonlinear simulation methodology for investigating the coupling effect of the manufacturing process and the TCT. The plastic and creep behaviors of the solder μbump are considered in the finite element modeling. The concerned geometric dimensions and underfill materials are also parametrically analyzed. Furthermore, the inelastic strain accumulated in the crucial SnAg solder μbump is examined. Results indicate that the residual strain in the manufacturing process causes an obvious packaging warpage and converges at the subsequent TCT stage. The creep of the solder μbump increases up to 50% in thermal cycling, thereby highlighting the importance of considering the creep model. Moreover, the parameterization of chip thickness can minimize the inelastic strain increment of the solder μbump, and the low Young's modulus of the underfill materials exerts a significant effect on the warpage of the packaging module and the stress compliance of the μbumps.

Electrodeposition of (111)-oriented and nanotwin-doped nanocrystalline Cu with ultrahigh strength for 3D IC application

The mechanical performance of electroplated Cu plays a crucial role in next-generation Cu-to-Cu direct bonding for the three-dimension integrated circuit (3D IC). This work reports direct-current electroplated (111)-preferred and nanotwin-doped nanocrystalline Cu, of which strength is at the forefront performance compared with all reported electroplated Cu materials. Tension and compression tests are performed to present the ultrahigh ultimate strength of 977 MPa and 1158 MPa, respectively. The microstructure of nanoscale Cu grains with an average grain size around 61 nm greatly contributes to the ultrahigh strength as described by the grain refinement effect. A gap between the obtained yield strength and the Hall–Petch relationship indicates the presence of extra strengthening mechanisms. X-ray diffraction and transmission electron microscopy analysis identify the highly (111) oriented texture and sporadic twins with optimum thicknesses, which can effectively impede intragranular dislocation movements, thus further advance the strength. Via filling capability and high throughput are also demonstrated in the patterned wafer plating. The combination of ultrahigh tensile/compressive strength, (111) preferred texture, superfilling capability and high throughput satisfies the critical requirement of Cu interconnects plating technology towards the industrial manufacturing in advanced 3D IC packaging application.

(Invited) Advanced ALD Applications

CMOS device feature size down-scaling is still continuous. Nowadays it reaches 5nm and beyond. The technology development in semiconductor industry encounters many new challenges. As consequences, new materials and new techniques are required to meet the challenges.At 45nm technology node, Atomic Layer Deposition (ALD) is introduced for gate stack process. Since then ALD is being used more and more in advanced technology nodes because of its intrinsic process features, e.g. accurate thickness control and excellent step coverage etc. Especially for the reduced feature sizes, ALD exhibits as a powerful technique, not only in gate stack, but also in advanced patterning process (SADP and SAQP) and advanced metallization barrier materials etc.Hf-based hik material deposited by ALD is widely used in logic gate stack and memory capacitor. Recently Hf-based materials are continuously getting more attentions due to its intrinsic features. It is reported that Hf-based materials can exhibit different resistor stage. Therefore it can be used as memristor in ReRAM. People also report Hf-based materials can be crystalized into orthorhombic phase and thus exhibit ferroelectric characteristics[1,3]. Based on this feature, it can be used in NCFET and FeRAM. In this paper, we can going to review the applications of Hf-based materials deposited by ALD in new memory fields.Although device down-scaling is still going on, the challenges are tremendous. As an alternative, 3D-IC packaging, stacks different chip together and increases the packaging density and chip performance. Therefore, recently 3D-IC packaging is getting more and more attractive. However, there are many constrains in 3D-IC packaging, e.g. low thermal budget, high aspect ratio structure, excellent film quality etc.. ALD is gradually accepted in 3D-IC packaging due to its intrinsic features. In this paper, we are going to discuss some ALD applications in advanced 3D-IC packaging.REFERENCES[1] J. Müller et al, NanoLetters, vol. 12, no. 8, pp. 4318-4323, 2012.[2] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.[3] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.

(Invited) Microfluidic Electroless Interconnection (MELI) Process for Low-Temperature, Pressureless Chip Stacking Applications

Increasing demands for high-performance miniaturized electronic devices have driven the semiconductor industry toward finer pitch and higher interconnect density. Copper pillar has been widely adopted and is rapid becoming the mainstream bumping technology for high-density interconnections, such as 2.5D and 3D IC packaging. Thermo-compression bonding has been widely used for high-density copper pillar bumps because of its highly accuracy alignment and placement. However, the high heat and high force applied to the components during the bonding process often induce high thermal-mechanical stress that causes severe damage to the devices and low-k dielectric layers. Because the mechanical properties of porous, low-k materials decreases with lower dielectric constants, this issue will become more severe in the future when lower dielectric constant materials are employed. Therefore, it is imperative to develop a low-temperature, low-pressure bonding process. To address this issue, a novel Cu-to-Cu bonding process called microfluidic electroless interconnection has been developed. This novel process forms electroless metal interconnections as a replacement for solders, which eliminates all the reliability concerns involved with soldering. Specifically, the process is able to bond copper pillars at a low temperature without applied any pressure. The operating temperature of the process is around 80 °C, which is considerably lower than most bonding processes. Also, there is no need to apply any bonding pressure throughout the bonding process due to the proposed bonding scheme structure. In this way, the thermo-mechanical stress can be largely reduced to maintain the structural stability of packaging. Furthermore, the most exciting aspect of this new approach is the integration of microfluidic technology with the electroless plating process, which allows to precise control the flow of fluids in and out the stacked chip to achieve better bonding performance. The flow rate can quantitatively determined and the fluid flow can be adjusted for either batch or continuous-flow operations. The main objective of this work was to investigate the feasibility of the microfluidic electroless interconnection process in joining copper pillars as a promising route for a low-temperature, pressureless bonding process. First, the overall plating uniformity across the entire die surface at different stand-off heights of the stacked chips was investigated. Preliminary results demonstrated that, by selecting a proper flow rate, a high level of plating uniformity across the die was obtained regardless of the standoff heights. In addition to the electrolessly bonded joints, when the bonding interface was examined by scanning electron microscopy (SEM) and focus ion beam (FIB), it was confirmed that no voids or seams appeared on the bonding interface between the pillars, indicating that the two electroless Ni layers that grew on the opposite sides had merged completely into a single structure. The growth and bonding mechanism of the electroless interconnection process was investigated and characterized fully. The bonding interface and phosphorus distribution in the electroless Ni bonds were examined by an electron probe micro-analyzer (EPMA) to ascertain the effect of batch and continuous flow processing. Moreover, the results of direct shear test shows that the bond strength of the electroless Ni between the copper pillars was greater than the adhesion strength of the Cr layer. Further, it was found that the process has the ability to compensate not only for non-uniform copper surfaces, but also for the misalignment and height mismatch of copper pillars, which provides a competitive edge over other bonding methods. This innovative low-temperature, pressureless electroless bonding approach shows considerable promise for applications that require low stress and low thermal budget process.

Effect of Nanoparticles Addition on the Microstructure and Properties of Lead-Free Solders: A Review

With the development of microelectronic packaging and increasingly specific service environment of solder joints, much stricter requirements have been placed on the properties of lead-free solders. On account of small size effect and high surface energy, nanoparticles have been widely used to improve the microstructure and properties of lead-free solders. Therefore, the composite solders bearing nanoparticles have recently attracted wide attention. This article reviewed the recent research on SnAgCu, SnBi, and SnZn composite solder alloys and introduced the effect of nanoparticles on their microstructure, mechanical properties, wettability, and reliability. The mechanism of nanoparticles strengthening was analyzed and summarized. In addition, the shortcomings and future development trends of nanoparticle-reinforced lead-free solders were discussed, which is expected to provide some theoretical reference for the application of these composite solder in 3D IC package.

Improving thermal shock response of interfacial IMCs in Sn–Ag–Cu joints by using ultrathin-Ni/Pd/Au metallization in 3D-IC packages

The feasibility of novel ultrathin-Electroless Ni/Electroless Pd/Immersion Au (ultrathin-ENEPIG) metallization containing ultrathin electroless Ni layer for 3D-IC packaging application was evaluated by thermal shock test in this study. Via employing ultrathin-ENEPIG pad, the joints showed higher resistance against thermomechanical stress due to minor degradation in solder and the strength enhancement of interfacial IMC. In the as-fabricated joints, larger Sn grain formed in the ultrathin-ENEPIG joints in contrast to those in the conventional-ENEPIG one, which caused the distinct failure modes between two different systems under the test. Additionally, a dual-layer structure of high/low Ni–(Cu,Ni)6Sn5 and a single layer of low Ni–(Cu,Ni)6Sn5 could be observed in the conventional-ENEPIG and the ultrathin-ENEPIG joints, respectively, after testing. The dual layer (Cu,Ni)6Sn5 degraded the thermal shock performance of conventional-ENEPIG joints as a result of the weak bonding of interface between high/low Ni–(Cu,Ni)6Sn5 layers. However, through employment of ultrathin-ENEPIG substrates, the electroless Ni layer was completely exhausted and thus only one layer of low Ni–(Cu,Ni)6Sn5 intermetallic formed in the ultrathin-ENEPIG joints. The formation of dual-layer compound was suppressed and the fracture between layers was inhibited, leading to a stronger bonding at interface. Furthermore, the overall thickness of interfacial intermetallic compound was also reduced due to the suppression of high Ni–(Cu,Ni)6Sn5 layer. Influences of Ni thickness on the related mechanisms behind dual-layer intermetallic suppression and the Sn grain structure in ultrathin-ENEPIG joints were addressed and discussed in details.

A novel model for through-silicon via (TSV) filling process simulation considering three additives and current density effect

Through-silicon via (TSV) filling by electrochemical deposition is still a challenge for 3D IC packaging, and three-component additive systems (accelerator, suppressor, and leveler) were commonly used in the industry to achieve void-free filling. However, models considering three additive systems and the current density effect have not been fully studied. In this paper, a novel three-component model was developed to study the TSV filling mechanism and process, where the interaction behavior of the three additives (accelerator, suppressor, and leveler) were considered, and the adsorption, desorption, and consumption coefficient of the three additives were changed with the current density. Based on this new model, the three filling types (seam void, ‘V’ shape, and key hole) were simulated under different current density conditions, and the filling results were verified by experiments. The effect of the current density on the copper ion concentration, additives surface coverage, and local current density distribution during the TSV filling process were obtained. Based on the simulation and experimental results, the diffusion–adsorption–desorption–consumption competition behavior between the suppressor, the accelerator, and the leveler were discussed. The filling mechanisms under different current densities were also analyzed.

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests.

The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. Results of both TCT data and the simulation indicate that μ-bumps with residual SnAg solders can reach more than 1200 fatigue life cycles. Moreover, several important design factors in the present 3D-IC package influence μ-bump reliability. Analytical results show that the μ-bump’s thermo-mechanical reliability can be improved by setting proper chip thickness, along with a WLUF that has a low elastic modulus and a small coefficient of thermal expansion.