2D Discrete Wavelet Transform Research Articles

PANORAMA: A 3D Shape Descriptor Based on Panoramic Views for Unsupervised 3D Object Retrieval

We present a novel 3D shape descriptor that uses a set of panoramic views of a 3D object which describe the position and orientation of the object's surface in 3D space. We obtain a panoramic view of a 3D object by projecting it to the lateral surface of a cylinder parallel to one of its three principal axes and centered at the centroid of the object. The object is projected to three perpendicular cylinders, each one aligned with one of its principal axes in order to capture the global shape of the object. For each projection we compute the corresponding 2D Discrete Fourier Transform as well as 2D Discrete Wavelet Transform. We further increase the retrieval performance by employing a local (unsupervised) relevance feedback technique that shifts the descriptor of an object closer to its cluster centroid in feature space. The effectiveness of the proposed 3D object retrieval methodology is demonstrated via an extensive consistent evaluation in standard benchmarks that clearly shows better performance against state-of-the-art 3D object retrieval methods.

Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm

The line-based method has been one of the most commonly-used methods of hardware implementation of two-dimensional (2D) discrete wavelet transform (DWT). However, data buffer is required between the row DWT processor and the column DWT processor to solve the data flow mismatch, which increases the on-chip memory size and the output latency. Since the incompatible data flow is induced from the intrinsic property of adopted lifting-based algorithm, a decomposed lifting algorithm (DLA) is presented by rearranging the data path of lifting steps to ensure that image data is processed in raster scan manner in row processor and column processor. Theoretical analysis indicates that the precision issue of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. A memory-efficient and high-performance line-based architecture is proposed based on DLA without the implementation of data buffer. For an N × M image, only 2N internal memory is required for 5/3 filter and 4N of that is required for 9/7 filter to perform 2D DWT, where N and M indicate the width and height of an image. Compared with related 2D DWT architectures, the size of on-chip memory is reduced significantly under the same arithmetic cost, memory bandwidth and timing constraint. This design was implemented in SMIC 0.18µm CMOS logic fabrication with 32kbits dual-port RAM and 20K equivalent 2-input NAND gates in a 1.00mm × 1.00mm die, which can process 512 × 512 image under 100MHz.

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

The suitability of the 2D Discrete Wavelet Transform (DWT) as a tool in image and video compression is nowadays indisputable. For the execution of the multilevel 2D DWT, several computation schedules based on different input traversal patterns have been proposed. Among these, the most commonly used in practical designs are: the row---column, the line-based and the block-based. In this work, these schedules are implemented on FPGA-based platforms for the forward 2D DWT by using a lifting-based filter-bank implementation. Our designs were realized in VHDL and optimized in terms of throughput and memory requirements, in accordance with the principles of both the schedules and the lifting decomposition. The implementations are fully parameterized with respect to the size of the input image and the number of decomposition levels. We provide detailed experimental results concerning the throughput, the area, the memory requirements and the energy dissipation, associated with every point of the parameter space. These results demonstrate that the choice of the suitable schedule is a decision that should be dependent on the given algorithmic specifications.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128×128×128 fMRI volume image in 20 ms.

High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

A highly pipelined line-based one-level 2D discrete wavelet transform (DWT) VLSI design is proposed using two line-FIFOs in 5/3 wavelet type and performing with input speed up to 2 samples/cycle. Furthermore, a recursive multi-level wavelet decomposition architecture using a dual buffer scheme is proposed to reduce the memory for wavelet coefficients to 1/4 Tile size. The two proposals allow for a 2D DWT architecture for JPEG2000 that is both high-speed and memory-efficient.

High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing

This paper presents an efficient lattice structure based VLSI architecture of 2D discrete wavelet transform (DWT) for hierarchical image compression, which is scalable to extend to an arbitrary 2D DWT with M laps and J levels. The proposed architecture consists Of four 1D lattice filters, which processes in horizontal and vertical directions at the same time. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N/sup 2//2 to compute an N/spl times/N image because the even and odd rows are processed simultaneously. Compared to conventional approaches, the proposed architecture shows shorter period to complete 2D DWT while requiring relatively less hardware resources. Therefore, the proposed architecture can be applied in real-time video signal processing such as JPEG-2000 and MPEG4, which require high speed processing. The process schedule using the data dependency graph, performance, and the required hardware cost are discussed.

A fine-grain load-adaptive algorithm of the 2D discrete wavelet transform for multithreaded architectures

In this paper we develop a load-adaptive multithreaded algorithm to compute 2D Discrete Wavelet Transform (DWT) and its implementation on a fine-grain multithreading platform. In a 2D DWT computation, the problem sizes reduces at every decomposition level and the length of the emerging computation paths also vary. The parallel algorithm proposed in this paper, dynamically scales itself to the varying problem size. During any iteration, the ratio of the number of local threads to the number of remote threads issued by a processor can be adjusted to be greater than 1 by controlling the algorithm parameters. This approach provides an opportunity to interleave computation and communication without explicitly introducing idle cycles on waiting for the remote threads to finish. Experimental results are reported based on the implementations of the proposed algorithm on a 20 node emulated multithreaded platform, EARTH-MANNA, specifically designed for fine-grain multithreaded paradigms. We show that multithreading implementations of the proposed algorithm are at least 2 times faster than the MPI-based message passing implementations reported in the literature, assuming the same processor speed. We further show that the proposed algorithm and implementations scale linearly with respect to problem and machine sizes.

An efficient vlsi implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters

The paper presents a VLSI design rule, namely, an embedded instruction code (EIC), for the discrete wavelet transform (DWT). Our approach derives from the essential computations of DWT, and we establish a set of multiplication instructions, MUL, and the addition instruction, ADD. In addition, we propose a parallel arithmetic logic unit (PALU) with two multipliers and four adders, called 2M4A. With these requirements, the DWT computation paths can be calculated more efficiently with limited PALUs. Furthermore, since the EIC is operated under the PALU, the number of needed inner registers depends on the wavelet filters' length. Besides, the boundary problem of DWT has also been resolved by the symmetric extension. Moreover, the two-dimensional inverse DWT (2D IDWT) can be completed using the same PALU as for 2D DWT; the only changes needed to be made are the instruction codes and coefficients. Our chip supports up to six levels of decomposition and versatile image specifications, e.g., VGA, MPEG-1, MPEG-2 and 1024/spl times/1024 image sizes.

RNS-FPL merged architectures for orthogonal DWT

Novel, regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1D discrete wavelet transform (DWT) and 1D inverse discrete wavelet transform (1DWT) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. They are suitable to be considered as the core of 2D DWT processors for high data rate image processing applications.

Medical image compression by applying 3D DWT in PACS

The process of image compression in a practical Picture Archiving and Communication System (PACS) was discussed with detail. To fully reduce the inter-slice correlation existing in the volumetric image sets generated by CT and MR, 3D Discrete Wavelet Transformation (DWT) was introduced in our application. Instead of using a fixed quantizer of lossless low frequency and distinct loss of high frequency, an adaptive quantizer was devised taking MSE as the performance index. In the low frequency subband, DPCM was replaced withS+P transform to facilitate coding computation. Compared with JPEG or 2D DWT, our method is 20%–50% more efficient. Furthermore, preliminary tests showed that 33 dB may be the maximal distortion threshold for CT images.

VLSI architecture for fast 2D discrete orthonormal wavelet transform

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. In this paper, we present a parallel pipelined VLSI array architecture for 2D dyadic separable DWT. The 2D data array is partitioned into non-overlapping groups of rows. All rows in a partition are processed in parallel, and consecutive partitions are pipelined. Moreover, multiple wavelet levels are computed in the same pipeline, and multiple DWT problems can be pipelined also. The whole computation requires a single scan of the image data array. Thus, it is suitable for on-line real-time applications. For anN×N image, anm-level DWT can be computed in $$\tfrac{{N^2 }}{{2_q }} + 2^{m - 1} (2p + 3)$$ time units on a processor costing no more than $$\tfrac{8}{3}(C_m + C_u )p(p + 2q)$$ , whereq is the partition size,p is the length of corresponding 1D DWT filters,Cm andCa are the costs of a parallel multiplier and a parallel adder respectively, and a time unit is the time for a multiplication and an addition. Forq=N ? m, the computing time reduces to $$\frac{N}{2}$$ . When a large number of DWT problems are pipelined, the computing time is about $$\tfrac{{N^2 }}{{2_q }}$$ per problem.