VLSI architecture for fast 2D discrete orthonormal wavelet transform

Abstract

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. In this paper, we present a parallel pipelined VLSI array architecture for 2D dyadic separable DWT. The 2D data array is partitioned into non-overlapping groups of rows. All rows in a partition are processed in parallel, and consecutive partitions are pipelined. Moreover, multiple wavelet levels are computed in the same pipeline, and multiple DWT problems can be pipelined also. The whole computation requires a single scan of the image data array. Thus, it is suitable for on-line real-time applications. For anN×N image, anm-level DWT can be computed in $$\tfrac{{N^2 }}{{2_q }} + 2^{m - 1} (2p + 3)$$ time units on a processor costing no more than $$\tfrac{8}{3}(C_m + C_u )p(p + 2q)$$ , whereq is the partition size,p is the length of corresponding 1D DWT filters,Cm andCa are the costs of a parallel multiplier and a parallel adder respectively, and a time unit is the time for a multiplication and an addition. Forq=N ? m, the computing time reduces to $$\frac{N}{2}$$ . When a large number of DWT problems are pipelined, the computing time is about $$\tfrac{{N^2 }}{{2_q }}$$ per problem.