8-bit Arithmetic Logic Unit Research Articles

AC Computing Methodology for RF-Powered IoT Devices

In this paper, an alternating current (ac) computing methodology is proposed for integration into wirelessly powered devices, such as radio-frequency (RF) tags and sensor nodes. Contrary to the traditional platforms that integrate direct current (dc)-powered computational logic along with the rectification and regulation stages, in the proposed approach, the harvested RF signal is directly used to power the data processing circuitry by leveraging the charge-recycling and adiabatic circuit theory. A near-field-based wireless power harvesting system with an 8-bit arithmetic logic unit is developed to evaluate the proposed framework. Simulation results in 45-nm technology demonstrate that the overall power consumption can be reduced by up to 16 times as compared to the conventional approach that relies on ac-to-dc conversion and static CMOS logic. This reduction in power enables significant computation capability for the RF-powered devices. Several important characteristics, such as the impact of circuit size on overhead and processing power, impact of voltage scaling on circuit operation, and power consumption, are investigated. Some important design issues and related tradeoffs are also discussed.

High Performance ALU Using Carry Look-ahead Adder

A Low Power 8-bit Arithmetic Logic unit (ALU) using a Carry look-ahead adder (CLA) and placing Low Vt (LVt) cells in Critical path is anticipated. The ALU is designed in 90nm CMOS technology. ALU is the most essential circuit in any processor. It consists of AE, LE, CLA and CE. This ALU is designed to calculate Arithmetic and Logical operations. Power and Delay values of different 8-bit adders like CLA, Sparse and Ripple Carry Adder (RCA) are designed and compared. The simulation results show that the design of ALU using CLA and incorporating High Vt and Low Vt cells in the CLA gives more power and delay efficient than with only Standard threshold voltage cells.

Complementary Logic Implementation for Antiferromagnet Field-Effect Transistors

In this paper, a compact and complementary logic implementation is proposed for antiferromagnet field-effect transistor (AFMFET) devices. The implementation enables a complete set of Boolean operations based on complementary logic as well as majority-gate logic. The impacts of several key device-level design parameters are investigated, such as the channel resistance and critical switching voltage, and their optimal values that minimize the overall energy-delay product (EDP) of a 32-bit arithmetic logic unit are quantified. In addition, it is shown that one can potentially take advantage of the large domain size of some AFM materials such as chromium and build a compact majority-gate-based logic. The potential performance benefits of the majority-gate-based logic are also quantified. Compared to the conventional CMOS logic circuit, the one with AFMFET devices using majority gates can potentially achieve $10\times $ improvement in terms of the EDP.

BCB Evaluation of High-Performance and Low-Leakage Three-Independent-Gate Field-Effect Transistors

Three-independent-gate field-effect transistors (TIGFETs) are a promising next-generation device technology. Their controllable-polarity capability allows for superior design of arithmetic and sequential logic gates. In this paper, the TIGFET technology has been benchmarked against several beyond-CMOS devices. The benchmarking techniques followed a similar approach used by the Nanoelectronic Research Initiative Group. The performance of the 32-bit adder and the 32-bit arithmetic logic unit (ALU) was investigated using the advanced 15-nm technology node. The TIGFET devices were shown to achieve the best energy-delay product (EDP) compared with all other beyond-CMOS devices for the 32-bit adder and competitive EDP for the 32-bit ALU. In particular, TIGFETs have 3.83 times and 1.54 times lower EDP than CMOS high-performance (HP) for the 32-bit adder and the 32-bit ALU, respectively. In addition, TIGFETs were shown to have a similar throughput for the 32-bit ALU compared with CMOS HP. Finally, due to TIGFETs’ ultralow leakage current and unique circuit designs, our results show that the standby energy of the 32-bit adder decreased by two orders of magnitude compared with CMOS HP and a decrease of at least one order of magnitude compared with CMOS low-voltage.

Reconfigurable arithmetic logic unit designed with threshold logic gates

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.

Resource Utilization Optimization with Design Alternatives in FPGA based Arithmetic Logic Unit Architectures

Designing Arithmetic Logic Unit (ALU) is a combinational logic problem. As ALU has a regular pattern, it can be broken into identical stages connected into cascade through carry chain. We have designed one stage of ALU and then duplicated it depending upon the size required. The design has been tested for 4, 8, 16, 32 and 64- bit width. The idea is resource sharing and functionality sharing technique to design an ALU that leads to a significant saving of resources. Different functionality has been obtained by using a single resource (parallel adder) with different inputs at different times through control circuit. The design through this approach leads to a significant reduction in hardware requirement. The design is implemented in 3s700anfgg484-4 FPGA. Significant reduction in hardware has been achieved. The hardware used has been compared with normal function by function design. Resources saving of 66% have been observed for 4-bit wide ALU implementation on FPGA. For 8 and 16-bit implementation the saving obtained is 65%. A hardware saving of 60% has been obtained for 32 and 64-bit implementation.

Implementation and Analysis of Reversible logic Based Arithmetic Logic Unit

There is a tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI). It however raises a question of sustainability of Moore's law due to almost intolerable levels of power consumption. Researchers have invented a lot of methods to reduce power consumption and recent technologies are switching to reversible logic. Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. Arithmetic Logic Unit (ALU) is considered to be the basic building block of a CPU in the computing environment and portability in computing system highly demands reversible logic based ALU. Modern processors usually have a word length of 32 or 64 bits. Divide and conquer approach principle cascades n number of 1 bit ALU to implement n bit ALU. Several researchers have proposed 1-bit ALU design using various reversible logic gates. This paper aims at categorizing various ways of implementation in VHDL using Xilinx ISE design suit 14.2 tool and comparative analysis of existing 1 bit ALU designs in terms of optimization metrics like power consumption, number of gates, number of constant inputs, number of garbage outputs and quantum cost. ALU realized using carry save adder block is found to be most optimum design in terms of gate count and quantum cost.

Design of Low Power 4-bit ALU Using Adiabatic Logic

This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and comparisons have been made. The analysis is carried out using the industry standard EDA design environment using 250 nm technology libraries from Tanner. The results prove that the CEPAL 4-bit ALU is 55% more power efficient than the CMOS 4-bit ALU at 100MHz and at 2.5V operating voltage.

8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations

This paper describes the design and testing of an 8-bit asynchronous wave-pipelined sparse-tree Rapid Single Flux Quantum (RSFQ) Arithmetic Logic Unit (ALU). Compared to previously developed RSFQ ALUs, this unit features an extensive set of 8 arithmetic and 12 logical operations. The execution of ALU operations consists of two steps. First, when necessary, one or both operands are inverted, and then operations are performed on these pre-processed data. Unlike the RSFQ Kogge-Stone-based designs, our parallel-prefix sparse-tree ALU has significantly reduced circuit complexity while maintaining robust operational margins at high frequency. An 8-bit ALU has been implemented with the International Superconductivity Technology Center (ISTEC) 10 kA/cm2 1.0 μm 9-metal ADP2.1 fabrication process as a joint effort between Stony Brook University, Yokohama National University, and Nagoya University. Using the CONNECT cell library and SFQ CAD tools developed at Nagoya and Yokohama, the Stony Brook team has developed a complete logical and physical design of the ALU chip. The 8-bit ALU core (without SFQ-to-dc and dc-to-SFQ converters) consists of 8832 Josephson junctions with an area of 7.2 mm2. Simulations show that the ALU can operate at the maximum rate of 42 GHz. It has the latency of 374 ps at a bias voltage of 2.5 mV. The chip was fabricated and tested at low frequency in 2012. Testing results showed malfunctioning of some gates but despite these shortcomings we still verified several ALU operations with the measured DC bias voltage margins of ±1.8%.

VHDL Implementation of 8-Bit ALU

In this paper VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1's and 2's complement operations and compare. ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 8-bit fast adder with 2's complement circuit to perform subtraction and logic gates to perform logical operation. The maximum propagation delay is 13.588ns and power dissipation is 38mW. The ALU was designed for controller used in network interface card.

20GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

Abstract We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES’ standard 4.5 kA/cm2 process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and high-speed test results for the 8-bit ALU circuit.

8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

We have designed and demonstrated an Arithmetic-Logic Unit (ALU) based on RSFQ technology as a required step toward building an 8-bit RSFQ processor datapath. The circuit was designed and fabricated with HYPRES' standard 4.5 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> process. The target clock frequency of the ALU is 20 GHz. In this paper, we present the design and functionality (low-speed) test results of the 8-bit ALU.

Fabrication Technique of Single Flux Quantum ALU by Using Nb Trilayer

Nb trilayer process has been serving as the most stable fabrication process of the Josephson junction integrated circuits for more than two decades. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipment. In this work, we took an advantage of those advanced fabrication equipments in developing a superconducting arithmetic logic unit (ALU) by using Nb trilayers. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for SiO2 depositions. Various dry etching techniques were used to define Josephson junction areas and various patterns of metallic and insulating layers. Our Nb films were stress-free and had the Tc's above 9 K. To enhance the step coverage of Nb films we used reverse bias DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens gigahertz clock frequency. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at 5 GHz clock frequency.

A rapid single flux quantum 1 bit arithmetic logic unit constructed with a half-addercell

We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1bit arithmetic logic unit (ALU) block. The circuit consists of three DC currentdriven SFQ switches and a half-adder. We successfully tested the half-addercell at clock frequency up to 20 GHz. The switches were commutating outputports of the half-adder to produce AND, OR, XOR, or ADD functions. For ahigh-speed test, we attached two switches at the input ports of the half-adderto control the high-speed input data by low-frequency pattern generators. Theoutput in this measurement was an eye-diagram. Using this set-up, the circuit wassuccessfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES1 kA cm−2 Nb Josephson junction fabrication process.

4980821 Stock-memory-based writable instruction set computer having a single data bus

A computer is provided as an add-on processor for attachment to a host computer. Included are a single data bus, a 32-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program memory addressing logic, micro-program memory, and a micro-instruction register. Each machine instruction contains an opcode as well as a next address field and subroutine call/return or unconditional branching information. The return address stack, memory addressing logic, program memory, and microcoded control logic are separated from the data bus to provide simultaneous data operations with program control flow processing and instruction fetching and decoding. Subroutine calls, subroutine returns, and unconditional branches are processed with a zero execution time cost. Program memory may be written as either bytes or full words without read/modify/write operations. The top of data stack ALU register may be exchanged with other registers in two clock cycles instead of the normal three cycles. MVP-FORTH is used for programming a microcode assembler, a cross-compiler, a set of diagnostic programs, and microcode.

Rapid integrated-circuit reliability-simulation and its application to testing

A reliability simulator which predicts electromigration through high-level simulation is presented. Although the accuracy of the voltage and current waveforms is decreased, the rapid simulation allows larger ICs and longer input vectors to be simulated. The decreased accuracy in determining node voltages is traded against improved accuracy in modeling the input workload. Three applications which were not feasible with earlier approaches are described: (1) a bit-serial processor is simulated for a specific application, computing the impact of individual instructions on the overall reliability; (2) the relative probabilities of all possible electromigration failures in a 4-bit arithmetic-logic unit were used to weight the coverage of random testing for that chip to predict the actual coverage experienced in the field; (3) an experiment determined the influence of the order of application of vectors during burn-in on the effectiveness of a screening operation. >

The Aleph trigger supervisor

The prototype of a FASTBUS master/slave, which in the Aleph experiment is the intelligent interface between the trigger system and the readout controllers, is described. It is based on two microprogrammable sequencers, one acting as a FASTBUS master and the other equipped with a 32-bit ALU (arithmetic logic unit); its internal registers/devices are time-shared by the two sequencers. The control part of the main protocol is implemented as two finite-state machines based on the PAL technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS/bipolar circuits for 60-MHz digital processing

High-performance bipolar/CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 4-GHz cutoff frequency is combined with standard CMOS devices on the same chip, has been applied to a processor. The design strategy was to provide high integration density using the CMOS circuit and accelerate the critical paths using the Hi-BiCMOS circuits. Hi-BiCMOS circuits with low-voltage swing have been developed and applied to a 32-bit arithmetic logic unit and a 128-kb ROM with bipolar drivers to drive a heavy load capacitance. A 17-ns 32-bit carry propagation delay time and a 17-ns ROM access cycle time have been achieved using 2-/spl mu/m Hi-BiCMOS technology. A minicomputer CPU with a 60-MHz machine cycle can be implemented with these circuits.

Self-Aligned Phosphorus Doped Polysilicon Gate MOS Device Radiation Hardening

It is well known that processing steps strongly affect the radiation tolerance of MOS oxides. In this paper we present the effects of the ion implantation to form the source-drain regions of self-aligned polysilicon gate MOSFETs. Radiation hardness varies systematically with the n+ and the p+ ion implantation energies, and the masking polysilicon gate thickness. For a fixed polysilicon thickness, there is an optimum implantation energy allowed to give the best device performance and radiation behavior. Extending the implantation energy beyond the optimum tends to degrade the hardness. This is verified by the capacitor experiments. The shift in n-channel threshold for devices fabricated by the optimum radiation-hardened process developed here is decreased from -6.1V to -1.8V at 3 × 105 rads (Si) total dose. The p-channel threshold at 1 × 106 rads (Si) is decreased by 4.5 volts. The 8-bit Arithmetic Logic Unit (ALU) device from wafer to wafer, and lot to lot can be operated well up to 1 × 106 rads (Si).

The Effect of Gate Oxide Thickness on the Radiation Hardness of Silicon-Gate CMOS

Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells. Devices with gate oxide thicknesses of 400, 570 (standard), and 700 A were fabricated. Irradiations were done at a dose rate of 2 × 106 rads (Si) per hour. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Between a linear and squared relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured. Maximum power supply current after irradiation was reduced by an order of magnitude for the thinnest oxide. The speed degradation of parts after 1 × 106 rads (Si) was reduced by 30 percent. Dose rate and annealing behavior at room temperature were also studied. A dose rate of 1 × 103 rads per hour results in no increase in power supply current. The speed change was similar to high dose rate plus anneal. Annealing after high dose rate (2 × 106 rads (Si) per hour) results in recovery of the N-channel threshold towards accumulation. Functionally, power supply current decreases and the parts slow down with time after irradiation. Thinning gate oxide of the silicon-gate CMOS results in better radiation hardness for all annealing studies as well.