Abstract
A reliability simulator which predicts electromigration through high-level simulation is presented. Although the accuracy of the voltage and current waveforms is decreased, the rapid simulation allows larger ICs and longer input vectors to be simulated. The decreased accuracy in determining node voltages is traded against improved accuracy in modeling the input workload. Three applications which were not feasible with earlier approaches are described: (1) a bit-serial processor is simulated for a specific application, computing the impact of individual instructions on the overall reliability; (2) the relative probabilities of all possible electromigration failures in a 4-bit arithmetic-logic unit were used to weight the coverage of random testing for that chip to predict the actual coverage experienced in the field; (3) an experiment determined the influence of the order of application of vectors during burn-in on the effectiveness of a screening operation. >
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