300-mm Wafer Research Articles

A WAFER PLANT FOR SINGAPORE

SAMSUNG ELECTRONICS AND Siltronic, the silicon wafer business of Germany's Wacker Chemie, are forming a joint venture to construct a $1 billion plant in Singapore for 300-mm silicon wafers. Construction is set to begin in August, following relevant regulatory approvals, and is expected to be completedby mid-2008. The firms say the plant's output will reach 300,000 wafers per month by 2010. Both companies will operate the 50-50 joint venture, which will be located near an existing Siltronic facility. Siltronic's parent, Wacker, will supply hyperpure porycrystalline silicon raw material for the wafers. In electronics manufacturing, many semiconductor chips are made at one time on a single silicon wafer. The semiconductor industry has been gradually replacing 200-mm wafers with 300-mm wafers as a way to increase chip output. Samsung says the new plant will provide a steady supply of 300-mm wafers for its own semiconductor fabrication. A first in the wafer industry, this ...

A Survey of Automated Material Handling Systems in 300-mm Semiconductor Fabs

The fast-paced developments and technological breakthroughs in the semiconductor manufacturing industry elevates the importance of optimum utilization of resources. The newer 300-mm wafers fabs place a high level of emphasis on increasing yield and reducing cycle times. Automated material handling systems are importanttools that help us achieve these objectives. In addition, due to the increased weight and size of 300-mm wafers, an automated material handling system isa must for a 300-mm manufacturing facility. This paper discusses various approaches for automated materials handling in semiconductor manufacturing industries.

Diffraction-limited performance of flat-substrate reflective imaging gratings patterned by DUV photolithography

We report on the first demonstration of flat substrate imaging gratings fabricated by deep ultraviolet (DUV) photoreduction lithography, which uniquely offers sub-100-nm resolution and spatial coherence over centimeter scales. Reflective focusing gratings, designed according to holographic principle, were fabricated on 300-mm silicon wafers by immersion DUV lithography. Spatial coherence of the fabrication process is evident in measured diffraction-limited imaging function. Flat-substrate gratings, with lines of arbitrary spacing and curvature, offer both dispersion and general spatial wavefront transformation combining the function of multiple optical elements. Fabrication at the sub-100-nm resolution level allows high-line-count, low-order efficient gratings even into the deep ultraviolet region. Nanoreplication of gratings at the wafer level provides a pathway to devices of ultimate low cost.

Characterization and control of microcontamination for advanced technology nodes and 300-mm wafer processing: overview and challenges

Advanced process technologies have been introducing many unseen problems on process yield and device reliability. Microcontamination, which enables defects causing electric faults, has also been hard to understand, detect, and control. In this paper, the requirements and methodologies for contamination control in advanced technologies such as at the 90-nm processing technology node and immersion lithography using 300-mm wafer processing were addressed. Combining techniques of vapor phase decomposition (VPD) and wafer outgassing system (WOS) for characterizing the very low levels of surface metallic and organic contaminants on 300-mm wafers makes a front-end process capable of realizing and deploying the necessary controls. Applying liquid chromatography-mass spectrometry (LC-MS) in the identification of contaminants of immersion fluids is a new experience for 193-nm lithography technology. Furthermore, the wafer-environment contamination controls, such as airborne molecular contaminants (AMCs), process critical material assurance and point-of-use quality are reviewed in the paper. This paper concludes by discussing the challenges for characterization and control of microcontamination in future manufacturing technologies.

Theoretical and experimental study of the formation of grown-in and as-grown microdefects in dislocation-free silicon single crystals grown by the Czochralski method

A complex theoretical and experimental investigation is performed, including the following stages. (i) Simulation of the processes of the recombination of intrinsic point defects and the formation of grown-in microdefects in dislocation-free Si single crystals 200 mm in diameter grown in modern commercial heating units. The simulation takes into account the thermal history of the defect growth. Modified designs of heating units are analyzed to compare the results of the simulation of thermal processes during the growth of Si single crystals 200 mm in diameter with a shield in the crucible region. The thermal history of the crystal is simulated, the recombination of intrinsic point defects near the crystallization front is analyzed, and the formation of vacancy microdefects in the temperature range t = 1200–900°C is modeled. This simulation made it possible to determine the effect of a heat shield on the processes of v-i recombination and microdefect formation. (ii) Microdefects in s-grown crystals and in crystals subjected to thermal treatments are investigated by optical and electron microscopy; specific features of the generation and motion of dislocations are analyzed for Si wafers containing microdefects of different types, formed as a result of the decomposition of the supersaturated solid solution of oxygen during multistep heat treatments of Si wafers. (iii) The three-dimensional problem of determining the field of elastic stresses caused by the wafer weight is solved in the isotropic approximation for 200-and 300-mm Si wafers placed on three or symmetrically arranged point supports of different areas.

Metaheuristic Scheduling of 300-mm Lots Containing Multiple Orders

The standard unit of transfer in new semiconductor wafer fabrication facilities is the front opening unified pod (FOUP). Due to automated material handling system concerns, the number of FOUPs in a wafer fab is kept limited. Moreover, a certain number of new and larger 300-mm wafers will be placed in these FOUPs and this makes grouping orders from multiple customers into a job a necessity. Thereby, efficient utilization of the FOUP capacity while attaining good system performance is a challenge. We previously investigated optimization-based solution approaches for minimizing total weighted completion time and maximizing on-time delivery performance for the single machine multiple orders per job scheduling problem. We present two metaheuristic solution approaches for this scheduling problem under two different typical wafer fab machine environments: single unit processing and single lot processing. Experimental results demonstrate that the metaheuristic approaches can find near-optimal solutions for realistic-sized 300-mm scheduling problems in an acceptable amount of computation time.

Low-cost wafer bumping

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnect technology. These processes differ significantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Factory Throughput Improvements Through Intelligent Integrated Delivery in Semiconductor Fabrication Facilities

Integrated Delivery is a system that integrates the automated material handling systems (AMHS) with process tools to automate the flow of material through a semiconductor fabrication facility (fab). It was developed to streamline operations in fully mechanized 300-mm wafer fabs by automating the delivery of lots to/from the tools, and automating all aspects of lot processing, with no manual intervention. Within this context, lot delivery performance is a critical factor impacting factory throughput. Poor material delivery performance translates into tools sitting idle waiting for lots to be delivered, which increases tool cycle time and decreases output. This work describes intelligent integrated delivery (IID) capabilities, including just-in-time proactive material movement and delivery prioritization, to reduce delivery time impacts. These capabilities significantly reduce the lot delivery queue time, and as a result, measurably improve factory throughput. The results have been demonstrated via theoretical modeling, as well through actual deployment in Intel's 300 mm fabs.

Selected implications of photoresist processing in 300-mm manufacturing

We discuss implications currently relevant to 300-mm resist processing in lithography. The large size of the wafers, and therefore the large volume of machine modules and media within these modules, demand tighter specifications and a careful reconsideration of design. We investigate a novel resist development process based on a new developer dispense nozzle. The critical dimension (CD) uniformity across the 300-mm wafer thus achieved is compared to a common process. Based on this, we are able to make a preliminary recommendation for the photoresist development technology required for future, high-end semiconductor device manufacturing. Resist thickness fluctuations around the edge area of a silicon wafer typically occur if high spin speeds are applied during the photoresist coating process. The 300-mm coating processes are particularly prone to the occurrence of such spin marks because the operating range of applicable spin speeds is lower in comparison to processes applied to wafers of lower diameters. In our example, we show how such local resist thickness fluctuations impact the product yield. Finally, a special type of micromasking defect is found to be particularly relevant to 300-mm lithography layers. This "doughnut-type" defect detracts the yield of the semiconductor product. The defect has a distinct physical appearance and is precipitated onto the wafer as a hollow resin sphere. This defect is not yet observed in our 200-mm reference process. The occurrence of the defect directly depends on the matching of the air flows entering and leaving the 300-mm coater cup. The mechanism of formation involves the presence of a photoresist-solvent aerosol.

Evaluation of Transistor Property Variations Within Chips on 300-mm Wafers Using a New MOSFET Array Test Structure

A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and across a 300-mm wafer. The evaluation system was established with a conventional parametric tester and dc power supplies suitable for application on production lines. It was observed that threshold voltage (V/sub th/) variations increased with the reduction of the channel area. A difference was also observed in the standard deviation (/spl sigma//sub vt/) between NMOS and PMOS. From statistical evaluations, controlling CDs and improving rolloff characteristics were found to be important to reduce V/sub th/ variations.

Detection of unknown localized contamination on silicon wafer surface by sweeping-total reflection X-ray fluorescence analysis

A new interpretation of the data from Sweeping-TXRF (total reflection X-ray fluorescence) was proposed for the analysis of semiconductor contamination. Formerly, we focused on the accumulated spectrum that represents average concentration. In the proposed method, the individual spectra are also utilized to obtain rough mapping information for the entire wafer surface. Although the individual integration time of measurement is very short (4–8 s/spot), a limit of detection at the level of 10 10 atoms cm −2 is maintained for each spot. This method was used to analyze actual wafers that had particulate contaminants on them, and the capability of particle detection was demonstrated. In addition, this method simultaneously gives the average concentration by using the accumulated spectrum, as reported before. Dedicated software for Sweeping-TXRF is under development and has already achieved a throughput of ca. 30 min for 200-mm wafers and ca. 50 min for 300-mm wafers.

Virtual vehicle in the connecting transport automated material-handling system (AMHS)

In the connecting transport system, the time spent waiting for an empty vehicle is eliminated effectively and the work-in-process level can be reduced. Four different fixed vehicle types were used to carry out the wafers moving task. Thus, the automated material-handling system for a 300-mm wafer fab can be one of the three methods above or any mixture of these three connecting transport methods. However, no one method outperformed the others in all operational scenarios. A new concept of the virtual vehicle in the connecting transport automated material-handling system is proposed that can improve the task of moving wafers between bays and within each bay by a single system with interconnected lines. In this virtual vehicle environment, when the moving request is initiated, the wafers are assigned to the appropriate vehicle that can be changed to the vehicle type. Discrete-event simulation models are developed in eM-Plant™ and compared with the virtual vehicle through the fixed vehicle in the connecting transport automated material-handling system. Using the virtual vehicle, the simulation results show that the performance measures such as throughput, transport time, 95% transport time and waiting time can be improved for different flow rates of the environment.

Integrated Bake/Chill Module With In Situ Temperature Measurement for Photoresist Processing

Thermal processing of photoresist are critical steps in the microlithography sequence. The postexpose bake (PEB) steps for current DUV chemically amplified resists is especially sensitive to temperature variations. The problem is complicated with increasing wafer size and decreasing feature size. Conventional thermal systems are no longer able to meet these stringent requirements. The reason is that the large thermal mass of conventional hot plates prevents rapid movements in substrate temperature to compensate for real-time errors during transients. The implementation of advanced control systems with conventional technology cannot overcome the inherent operating limitation. An integrated bake/chill module with in situ temperature measurement capability has been developed for the baking of 300-mm silicon wafers. The system provides in situ sensing of the substrate temperature. Real-time closed-loop control of the substrate temperature is thus possible as oppose to conventional open-loop control of the substrate temperature. Experimental results are provided to demonstrate a complete thermal cycle.

Simulation studies and experimental verification of the performance of a lithocell combination bake-chill station

Simulation studies along with the necessary experimental verification of the performance of a new combination bake-chill station designed by FSI International in its POLARIS® thermal road-map project is presented in this paper. Since in this new design the 300-mm wafer is heated to the desired bake temperature and chilled back to room temperature before removed out of the station, a tight temperature control of the wafer throughout the process is achieved. To analyze the thermal performance of the station, an axi-symmetric model and a three-dimensional model geometrically similar to the new station are generated. The commercial CFD software Fluent® is employed to solve the Navier Stokes and energy equations in the computational domain. Experimental data as measured by a 42-point OnWaferTM temperature sensor wafer is used to verify the predictions of the simulated transient temperature behavior from the numerical model on the new station. Further, the simulations and experiments presented here substantiate the thermal agility of the proposed combination bake-chill station design. Higher throughput of the cluster, a major productivity improvement contribution of this new design, is also presented. Influence of the combination bake-chill station mechanical and thermal design losses on the wafer surface temperature uniformity and suggestions for improvements are also discussed.

Development of vapor phase decomposition-total-reflection X-ray fluorescence spectrometer

A total reflection X-ray fluorescence spectrometer integrated with vapor phase decomposition, VPD-TXRF, was newly developed. This instrument was designed to achieve a minimum footprint, to avoid cross contamination during operation, and to protect people and instruments from HF gas. Comparisons between analysis by VPD-TXRF and by atomic absorption spectrometry (AAS) indicated very good agreement in a wide range, from 10 8 to 10 12 atoms/cm 2. The lower limits of detection (LLDs) were improved by two orders of magnitude compared with straight TXRF. For 300-mm Si wafers, the LLDs were 5×10 8 atoms/cm 2 and 1×10 7 atoms/cm 2 for Al and Ni, respectively. VPD-TXRF was able to perform ultra-trace analysis at the level of 10 8 atoms/cm 2.

Czochralski's Creative Mistake: A Milestone on the Way to the Gigabit Era

Much of the rapid change in industry, science, and society is brought about by the meteoric development of the microelectronics industry. Daily life is affected by this development; one has only to think of mobile telephones and the chips on modern credit cards. The raw material for microelectronics is the single crystal of silicon, with very high purity and almost perfect crystal structure. About 95% of the world's current production of silicon single crystals is achieved using the process that Jan Czochralski discovered in 1916. Today, single crystals of silicon can be grown that are up to 2 m long, 300 mm in diameter, and weigh up to 265 kg. The use of magnetic fields has led to significant advances in crystal-drawing technology. Intensive research and development reveals that in addition to the technology, which provides crystals of ever-increasing diameter, defect engineering, and the control of the numerous temperature-dependent reactions of crystal defects, are of paramount importance.

Simulation of the stresses produced in large-diameter silicon wafers during thermal annealing

The three-dimensional problem of stress and strain fields in dislocation-free silicon wafers 200 and 300 mm in diameter placed horizontally on three symmetrical supports and subjected to is gravitational forces and thermal stresses formulated and solved in the isotropic approximation. Under the action of gravitational forces, a wafer is shown to have the lowest total stress when the supports are positioned at a distance of 0.6–0.7R from the center of the wafer. The shear-stress fields are calculated for all possible slip systems. The elastic-stress field in a 300-mm wafer is found to be induced mainly by gravitational forces even at a radial temperature gradient of 10 K. At this temperature gradient, the contribution from thermal stresses in a 200-mm wafer is comparable to the contribution from gravitational forces. At radial temperature gradients lower than 5 K, the contribution from thermal stresses can also be neglected for a 200-mm wafer. The maximum shear stresses calculated indicate that one should not neglect possible dislocation generation in the zone of contact between a wafer and the supports during high-temperature annealing of 200-mm and, especially, 300-mm wafers.

The evaluation of manual FOUP handling in 300-mm wafer fab

Semiconductor manufacturing industry is moving into the production of 300-mm wafers. To solve the increased workload problem in manual wafer handling, some personal guided vehicles (PGVs) have been developed to help in the transfer of front opening unified pods (FOUP). This study compares two kinds of PGVs with a traditional cart and evaluates the feasibility of using them for manual FOUP handling tasks. Manual FOUP handling capability was assessed. The results indicate that there is no obvious advantage in using any of the two evaluated PGV's over the manual cart. There is potential risk of causing musculoskeletal disorders for female operators to handle the 300-mm FOUP manually. Since the development of a fully automated intrabay FOUP handling system is a project of high technical difficulty, a combination of manual and automated handling is the current approach. To enhance the operator's health, safety and productivity, selection and training of operators, adequate design of handling tools and machine interface, assessment and balancing of workload are necessary.

Europe's semiconductor makers are back in the game

European chipmakers have bounced back after being declared nearly dead almost two decades ago - and despite one of the worst downturns in the global semiconductor industry. Three of the world's top 10 chipmakers are now European, compared with just one a decade ago, according to IC Insights Inc., a market research group (Scottsdale, Ariz.). The French-Italian venture STMicroelectronics NV (Geneva) is ranked fourth. Germany's Infineon Technologies AG (Munich), despite its dependence on the ravaged DRAM and telecom markets, claims sixth place. Royal Philips Electronics NV (Amsterdam) is tenth. Europe has shown a remarkable determination to retain control of enabling technology in integrated circuits and become competitive in this market. Its technology leaders have pushed through major restructuring, from consolidation to cooperation. Equally important, they have found not only new ways to manufacture chips but also new uses beyond computers. Introducing 300-mm wafers has been one of several reasons for the renewed success.

Performance of a high-productivity 300-mm dual-stage 193-nm 0.75-NA TWINSCAN™ AT:1100B system for 100-nm applications

To realize high productivity at the 100-nm node, ASML developed the TWINSCAN™ AT:1100B. This dual-stage 193-nm lithography system combines high throughput TWINSCAN™ technology for 300-mm wafers, excellent dynamical performance, and low-aberration 0.75-NA Starlith™ 1100 projection optics. The system is equipped with a 20-W 4-kHz ArF laser and the AERIAL™ II illuminator, enabling high intensity off-axis and multipole QUASAR™ illumination. Important process control requirements for the 100-nm technology node are CD variation across the chip and across the wafer. Full wafer leveling, including dies on the edge of the wafer, and CD uniformity performance on 300-mm wafers with and without topology are presented, showing full wafer CD uniformity numbers as low as 6.3 nm 3σ for 100-nm isolated lines with assisting features. Imaging performance of dense, fully isolated lines plus dense and isolated contact holes is shown. Also, printing of critical customer structures is discussed. With these results it is demonstrated that the TWINSCAN™ AT:1100B 300-mm ArF Step & Scan system meets the requirements for the 100-nm node.