Point FFT Research Articles

Performance Evaluation of OFDM System with Rician, Rayleigh, Rayleigh with Awgn and Awgn Channel for Bluetooth, Fixed and Mobile Wimax Application

The emergence of WIMAX has attracted interest from wireless communication researchers. This paper discusses the OFDM for wireless communication. It include Bit Error Rate and Symbol Error Rate versus the ratio of bit energy to noise power spectral density (Eb/No) for different communication channels like AWGN channel, Rayleigh multipath channel, combined Rayleigh multipath with AWGN channel and Rician channel. The simulation is designed on computer MATLAB 9 version with 64-point FFT. It demonstrates that AWGN has better performance than any other channel. The BER of AWGN channel is 10-5 at 8dB SNR for Rayleigh multipath channel is 10-4.5 at 40dB SNR for Rayleigh multipath channel with AWGN is 10-4 at 30dB SNR and for Rician channel is 10-3 at 30dB SNR. The SER of AWGN channel is 0.02 at 12dB and approximately 0 at 14dB whereas SER for Rayleigh multipath channel with AWGN is 0.0009 at 30dB. So, AWGN channel has better SNR than any other channel. It can be used for OFDM Bluetooth 802.11g-2003, fixed WIMAX 802.16-2004 and mobile WIMAX 802.16e-2005

DESIGN OF A REVERSIBLE FUSED 32-POINT RADIX -2 FLOATING POINT FFT UNIT USING 3:2 COMPRESSOR

This paper aims on the design of a reversible fused 32Point Radix-2 single precision floating point FFT unit using 3:2 compressor. The work focuses on the realization of three reversible fused floating point units: reversible floating point add-sub unit, reversible floating point multiply-add unit and reversible floating point multiply-subtract unit. The proposed work requires the design of a reversible single precision floating point adder, a reversible single precision floating point subtractor and a reversible single precision floating point multiplier. A reversible single precision floating point adder and subtractor is designed with less quantum cost, less number of reversible gates and less constant inputs. A reversible single precision floating point multiplier is implemented using 3:2 compressor as the 24x24 bit multiplier based on 3:2 compressor is highly efficient when compared with the design using 4:3 compressors. A reversible fused 32-Point Radix-2 floating point FFT Unit using 3:2 compressor consumes less number of resources, operates at a slightly greater speed and dissipates less power when compared with the reversible discrete 32-Point Radix-2 floating point FFT Unit. The proposed Fused 32-Point Radix-2 floating point FFT unit using 3:2 compressor dissipates 2.074W while the same design as a discrete implementation dissipates 2.176W.

Designing and Simulation of 32 Point Fft Using Radix-2 Algorithm for Fpga

The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the applications of the fast Fourier transform include Signal analysis, Sound filtering, Data compression, Partial differential equations, Multiplication of large integers, Image filtering etc. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). This paper concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation-In- Time (DIT) domain, Radix-2 algorithm, this paper uses VERILOG as a design entity. The input of Fast Fourier transform has been given by a keyboard using a test bench and output has been displayed using the waveforms on the Xilinx Design Suite 13.1 and synthesis results in Xilinx show that the computation for calculating the 32- point Fast Fourier transform is efficient in terms of speed. I. Introduction This proposes the design of 32-points FFT processing block. The work of the project is focused on the design and implementation of FFT for a FPGA kit. This design computes 32-points FFT and all the numbers follow fixed point format of the type Q8.23, signed type input format is used.The direct mathematical derivation method is used for this design. In this project the coding is done in VHDL (8) & the FPG synthesis and logic simulation is done using Xilinx ISE Design Suite 13.1. The Discrete Fourier Transform (DFT) plays an important role in the analyses, design and implementation of the discrete-time signal- processing algorithms and systems it is used to convert the samples in time domain to frequency domain. The Fast Fourier Transform (FFT) is simply a fast (computationally efficient) way to calculate the Discrete Fourier Transform (DFT). The wide usage of DFTs in Digital Signal Processing applications is the motivation to Implement FFTs. Almost every branch of engineering and science uses Fourier methods. The words frequency, period, phase, and spectrum are important parts of an engineer's vocabulary.The Discrete Fourier transform is used to produce frequency analysis of discrete non periodic signals. The FFT is another method of achieving the same result, but with less overhead involved in the calculations. Fig1:

A Novel Architecture for Radix-4 Pipelined FFT Processor using Vedic Mathematics Algorithm

The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. In this study, an efficient addressing scheme for radix-4 64 point FFT processor is presented. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix-4FFT.

Verilog Implementation of 32 Point FFT Using Radix-2 Algorithm on FPGA Technology

Verilog Implementation of 32 Point FFT Using Radix-2 Algorithm on FPGA Technology

Verilog Implementation of 32 Point FFT Using Radix-2 Algorithm on FPGA Technology

Verilog Implementation of 32 Point FFT Using Radix-2 Algorithm on FPGA Technology

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

Design and Implementation of a Large Points FFT Acceleration Unit in Multi-Processor System Based on FPGA

This paper introduces the design and implementation of a large points FFT acceleration unit of multi-processor system based on FPGA. It introduces radix-2 DIT-FFT algorithm and the features of hardware platform. It analyzes the FFT acceleration unit overall and divides it into several modules. Then hardware implementations of modules are discussed. The whole FFT acceleration unit is a part of one multi-processor image processing system and the whole system is tested by software and hardware co verification. Results are verified between the software simulation and Virtex6 evaluation board of Xilinx Company. The results are compatible in the range of error. The FFT acceleration unit meets the needs of the whole system and the design is successful.

Enhanced Hardware Efficient FFT Processor Based On Adaptive Recoding CORDIC

In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the bit error precision (BEP) of which is improved to 14 th . Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4us. DOI: http://dx.doi.org/10.5755/j01.eee.19.4.1422

Low Power R4SDC Pipelined FFT Processor Architecture

When the real-time signal processing is required pipelined FFT is the suitable option because of its high throughput and low power demands. A number of FFT architectures are there. Radix-4 single delay commutator (R4SDC) architecture is researched in this paper. R4SDC is the most popular pipeline FFT architectures, because of its efficient use of butterflies and multipliers. In this a low power technique for the pipeline FFT architecture is discussed. In this, Conventional R4SDC architecture, complex multiplier, and multiplier-less architecture based on common sub-expression technique are implemented and compared for 16, 64 and 256-point FFT architectures. A new type of multiplier algorithm called Multiplier-less architecture is implemented and compared with the carry save array, Wallace and Conventional complex multiplier (NBW).

Design and Implementation of Floating Point FFT Processor using VHDL

Design and Implementation of Floating Point FFT Processor using VHDL

The robustness of subcarrier-index modulation in 16-QAM CO-OFDM system with 1024-point FFT

We present in numerical simulations the robustness of subcarrier index modulation (SIM) OFDM to combat laser phase noise. The ability of using DFB lasers with SIM-OFDM in 16-QAM CO-OFDM system with 1024-point FFT has been verified. Although SIM-OFDM has lower spectral efficiency compared to the conventional CO-OFDM system, it is a good candidate for 16-QAM CO-OFDM system with 1024-point FFT which uses a DFB laser of 1 MHz linewidth. In addition, we show the tolerance of SIM-OFDM for mitigation of fiber nonlinearities in long-haul CO-OFDM system. The simulation results show a significant penalty reduction, essentially that due to SPM.

Design of 3780 Points FFT Processor for DTMB Receiver

In this paper, a design of FFT processor for Digital terrestrial multimedia/television broadcasting (DTMB) receiver is presented. This processor is based on mixed-radix algorithms, prime factor algorithms and Winograd Fourier Transform algorithm (WFTA). Due to the adopted in-place algorithm in this design, the area consumption of the processor is reduced, and the simulation shows that SQNR of the processor is 60.5dB on the condition that the input and output data are both 13 bits.

Applications of chirp z transform and multiple modulation zoom spectrum to pulse phase thermography inspection

The fine spectrum structure is required when some key frequencies are estimated; however the implementation may be hindered due to insufficient frequency resolution. In this work, two types of transforms were introduced into Pulse Phase Thermography (PPT), the first was Chirp Z Transform (CZT), which was used for the badly sampled or short truncated data, and the other was Multiple Modulation Zoom spectrum Analysis (ZFFT), used for the long duration data. The CZT can refine the spectrum and improve the frequency resolution; consequently the subtle spectral structure of the selected local band can be observed for purchasing the precise frequency; furthermore time consumption for long point FFT calculation can be greatly alleviated by the ZFFT without worsening the resolution. The comparative test results demonstrate that the proposed CZT can obtain more accurate characteristic frequencies; in addition, the reconstructive images from the developed method are better than the ones by conventional technique, simultaneously ZFFT can save calculation time and storage space largely.

Competent Realization of Co-Operative Spectrum Sensing in Cognitive Radio Systems

Cognitive radio is widely expected to be the next Big Bang in field of wireless communications. The objective of cognitive radio is to enhance the spectrum utilization efficiency. Spectrum sensing, a challenging task of cognitive radio helps in opportunistic spectrum access. Co-operative spectrum sensing mitigates these effects of fading, shadowing and uncertainties in normal sensing at the cost of energy consumption. Energy consumption in Co- operative spectrum sensing is due to computation of full spectrum FFT. This paper aims at the design of co-operative spectrum sensing unit in a cognitive radio system. It present a coprocessor for computing reduced point FFT, a block for the detection of spectrum hole, a fusion center for combining the decision from different users and a special prediction block for improving performance of Co-operative spectrum sensing. This idea reduces the computation to one fourth. The simulations are done using Xilinx ISE design suit 12.1 and ModelSim and synthesized using VerilogHDL.

AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE

In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements (PE). The proposed architecture can perform N-point FFT using only 4/3N delay elements and involves a latency of N/4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has been made to show the efficiency of the proposed design. Moreover, from the experimental results obtained from a FPGA prototype we find that the proposed design involves an execution time of 56% lower than that obtained with Xilinx IP core and an increase of 19% in the throughput by area ratio for 256-point FFT.

Implementation of Dynamic Reconfigurable Audio Player and Spectrum Analyzer

This work presents the implementation of FPGA based run time reconfigurable audio player system that is targeted to ML507 board with frequency component display of the stored audio data. The presented work combines both HW and SW flows where the complex parts of the architecture are designed to HW modules. These HW modules can be reconfigured on the fly by using partial dynamic reconfiguration. In our work, we are using filter block as partial reconfiguration module, 16 point FFT to decimate audio sample data in frequency in SW logic and displaying the spectrum of the audio signal on the display monitor. Our aim is to implement reconfigurable complex audio player as an application of reconfiguration computing, proving how this technique may be helpful to decrease resource utilization of the device with negligible performance overhead.

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

This paper presents a multimode FFT processor for wireless personal area network (WPAN), wireless local area network (WLAN), and wireless metropolitan area network (WMAN) applications. Using the proposed flexible-radix-configuration multipath-delay-feedback (FRCMDF) architecture, variable-length/multiple-stream FFTs capable of achieving a high throughput can be performed in a hardware-efficient manner. Based on the FRCMDF structure, a dual-optimized multiplication scheme is also proposed to further improve the area and energy efficiency. In addition, the proposed configuration scheme can provide an architectural support for power scalability across FFT modes. A test chip for the proposed FFT processor has been designed and fabricated using a TSMC-0.18 m CMOS process with a core size of 3.2 mm^2 and a signal-to-quantization-noise ratio (SQNR) of over 40 dB. When the FFT mode is configured to operate as a 2.4 GS/s 512-point FFT at 300 MHz, the measured power consumption is 507 mW. Compared with previous multimode FFT designs, our FFT chip is more area- and energy-efficient as it is able to provide relatively higher throughput per unit area or per unit power consumption. Also, the power scalability across FFT modes is relatively exhibited in the proposed FFT processor.

Zoom FFT를 이용한 정밀 레벨 측정 장치의 구현

Abstract: In this paper, level instrument is implemented using beat frequency for distance measurement which means the difference between Tx and Rx signal frequency from FMCW Radar Level Transmitter. Beat frequency is analyzed through Fast Fourier Transform of which frequency precision can be improvedby applying Zoom FFT. Distance precision is improved from 146.5[mm] to 5[mm] using the advantage ofZoom FFT which can raise the frequency precision without changing the sampling frequency or FFT pointnumber to be fixed in the beginning of designing signal processing. Also, measurement error can be reduced within 2[mm] by incresing the FFT points using the method of Spline interpolation.For verifying the effectiveness of this Zoom FFT to FMCW Radar Level Transmitter, test bench is made to measure thedistance for every 1[mm] between 700[mm] and 2000[mm] and measurement error can be checked in therange of ±2[mm]. Key words: FMCW Radar, Beat frequency, Zoom FFT, Decimation filter, Spline interpolation

A High Performance Implementation of Non-Power-of-Two FFT with EPUMA Platform

Non-power-of-two points FFT processing is becoming more and more important due to the loading of new communication standard. In this paper, three non-power-of-two points (1152, 1200, 1536) FFT are implemented with a parallel computing platform, ePUMA. Simulation results show that the proposed implementation achieve better performance compared with the commercial TI DSP processor. The proposed implementation method can be applied to other points FFT or convolution algorithms.