4-bit Flash Research Articles

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Novel Digital Background Calibration Technique for 16 bit SHA-less Multibit Pipelined ADC

In this paper, a high resolution of 16 bit and high speed of 125MS/s, multibit Pipelined ADC with digital background calibration is presented. In order to achieve low power, SHA-less front end is used with multibit stages. The first and second stages are used here as a 3.5 bit and the stages from third to seventh are of 2.5 bit and last stage is of 3-bit flash ADC. After bit alignment and truncation of total 19 bits, 16 bits are used as final digital output. To precise the remove linear gain error of the residue amplifier and capacitor mismatching error, a digital background calibration technique is used, which is a combination of signal dependent dithering (SDD) and butterfly shuffler. To improve settling time of residue amplifier, a special circuit of voltage separation is used. With the proposed digital background calibration technique, the spurious-free dynamic range (SFDR) has been improved to 97.74 dB @30 MHz and 88.9 dB @150 MHz, and the signal-to-noise and distortion ratio (SNDR) has been improved to 79.77 dB @ 30 MHz, and 73.5 dB @ 150 MHz. The implementation of the Pipelined ADC has been completed with technology parameters of 0.18μm CMOS process with 1.8 V supply. Total power consumption is 300 mW by the proposed ADC.

A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs

A 6-bit flash analog-to-digital converter (ADC) using reference-voltage-interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs the successive approximation algorithm and the minimized residue algorithm to determine precise calibration levels. Implemented by a 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at a 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 and 0.42 least significant bit, respectively. The power consumption is 25 mW at 2 GS/s from a 1.2 V supply. The core area is $0.32~{\mathrm{ mm}} \times 0.62$ mm, and the figure of merit is 0.34 pJ/conversion step.

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

Performance evaluation of a new single-ended comparator for low-power high-speed flash ADC

ABSTRACTIn this paper, a new single-ended comparator is explored for designing the reference ladder-free flash analog-to-digital converter (ADC). This proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage-generation method for producing the reference voltage for the flash ADC design. Employing optimised comparator gives various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate for system-on-chip ADC implementation. The basic structure of the single-ended comparator is a modified complementary metal oxide semiconductor (CMOS) inverter. The performance of the modified CMOS inverter circuit is compared with the CMOS inverter. Simulation results show that the modified CMOS inverter-based comparator achieves average power consumption of 1.46 μW with propagation delay of 53.8 ps. To demonstrate the functionality of the new comparator, a 4-bit flash ADC has also been realised. The designed 4-bit flash ADC exhibits significant improvement in terms of power and speed of previously reported flash ADCs. The converter consumes power 274 μW from a 1.8-V supply and achieves the conversion speed of 1 GHz in United Microelectronics Corporation 180-nm CMOS. The measurement of maximum differential and integral nonlinearities of the flash ADC are 0.2 least significant bit (LSB) and 0.6 LSB, respectively.

The Design of a High Speed Nonlinear Feedback-based Current Comparator

In this paper a new current comparator architecture is presented, which utilizes the concept of nonlinear feedback to speed up the operation. The analytical formulation for quantifying the effect of the feedback is put forward. The functionality of the proposed comparator is verified using simulations carried out on an Orcad Pspice tool using Taiwan Semiconductors Manufacturing Company (TSMC) 0.18 µm technology parameters. The resolution and delay are found to be ± 10 nA and 1.48 ns, respectively at a reference current of 1µA. The effects of parameter variations on the performance of the proposed comparator at different design corners is also studied. The usefulness of the proposed comparator is demonstrated through a 3-bit current mode flash Analog to Digital Converter (ADC) and its performance parameters are also calculated using simulations. The simulation results show that the 3-bit current mode flash Analog to Digital Converter exhibits no missing codes and has Differential Non-Linearity (DNL) of -0.25 Least Significant Bit (LSB) and Integral Non-Linearity (INL) of -0.19 LSB.

A 5.8 mW Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer

This paper presents a power-efficient realization of a third-order continuous-time delta-sigma $({\rm CT}-\Delta \Sigma)$ modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The ${\rm CT}-\Delta \Sigma$ modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed ${\rm CT}-\Delta \Sigma$ modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in ${\rm FOM}\_{\rm W} = 96.3$ fJ/level and ${\rm FOM}\_{\rm S} = 161$ dB.

A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder

The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion (TDC) technique is introduced which performs the complete conversion within a single clock cycle. The measurement results show that the proposed 5-bit converter achieves an 80MHz sampling rate while consuming 900μW of power from the 1.8V supply voltage. The prototype ADC is developed in a 180nm standard CMOS technology and achieves the power efficiency of 445fJ/conversion which is comparable to many existing state-of-the-art flash ADCs. The measured performance is achieved without any design optimization or circuit calibration techniques confirming the promising benefits of the proposed topology. Thanks to the fully-digital structure, the circuit enables a robust and compact implementation which is very convenient for interleaving and beneficial for many potential applications.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors – Design study in 180 nm and 40 nm CMOS

We report on the design of a 4-bit flash ADC with dynamic offset correction dedicated to measurement systems based on a pixel architecture. The presented converter was manufactured in two CMOS technologies: widespread and economical 180nm and modern 40nm process. The designs are optimized for the lowest area occupancy resulting in chip areas of 160×55µm2 and 35×25µm2. The experimental results indicate integral nonlinearity of +0.35/−0.21 LSB and +0.28/−0.25 LSB and power consumption of 52µW and 17µW at 5MS/s for the prototypes in 180nm and 40nm technologies respectively.

14‐bit 20 μW column‐level two‐step ADC for 640 × 512 IRFPA

A column-level two-step analogue-to-digital converter (ADC) structure for infrared focal-plane array (IRFPA) is proposed. The first step adopts a 16-column-shared 6-bit flash ADC to accomplish the coarse conversion of 16 columns one by one. Owing to the staggered code and correction, a dynamic comparator is adopted in the flash ADC and the power dissipation of a flash ADC averaged to one column in period is only 0.386 μW. The second step is SAR conversion of which the cycle time is prolonged. The input voltage variation of the comparator in the charge redistribution structure is decreased to tens of millivolts; so a 1.8 V power supply is adequate in spite of 5 V VFS. The power dissipation of this comparator is reduced to 5.966 μW. Also, the lower clock frequency of the SAR logic reduces the dynamic power. A 14-bit two-step ADC is designed in 0.18 μm process and the equivalent power dissipation of the proposed ADC structure for one column is <20 μW.

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, −0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

A 12-bit Hybrid Digital Pulse Width Modulator

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

&lt;b&gt;Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm 2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

A Reconfigurable 50-Mb/s-1 Gb/s Pulse Compression Radar Signal Processor With Offset Calibration in 90-nm CMOS

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution.

A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.

Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip

This paper presents design and implementation of a 12-GS/s fully differential data acquisition (DAQ) system-on-chip (SoC) fabricated in a standard 130-nm CMOS process. The proposed DAQ is comprised of a 4-bit flash ADC and four channels of 1:32 demultiplexer (DEMUX) with on-chip custom registers. At 12-GS/s sampling rate, the DAQ SoC achieves an SNDR of 19.2 dB for 2.9-GHz input signal and 24.2 dB for low-frequency inputs. The flash ADC and each DEMUX channel consume 200and 260-mA from 1.3 V supply and occupy an active area of 0.85 and 0.70 mm 2 , respectively. The DAQ SoC does not employ time interleaving and calibration techniques. In the meantime, no BWor speed-enhancing inductors have been used in the proposed system. The DAQ prototype achieves the highest sampling rate in 130-nm CMOS technology.

Design and Comparative Analysis of SRAM Cell Structures using 0. 5 µm Technology

In rapid development of digital designs, memory is the most important building block, as half of the silicon area is used to store data value and program instructions .The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption. Speed and power consumption is the key parameter in ADC resolution. In this paper, we design and analyze 4-bit flash ADC by using 0.5 μm CMOS technology in Tanner Tool. In the proposed design, we are using TIQ comparator and mux based encoder for converting analog signal in to digital signal, and analog input range is between 0 to 1.36V, with the supply voltage of 2.5V. Here we work on low power consumption of comparator which can be achieved by varying W/L ratio of PMOS and NMOS of TIQ comparator. The tool used for simulation purpose is S-Edit, TSpice, W-Edit by Tanner Tool using hp0.5μm CMOS technology at supply voltage of 2.5volts.