14nm FinFET Research Articles

State-of-the-Art High-Resolution 3D X-ray Microscopy for Imaging of Integrated Circuits

Abstract X-ray ptychography, as recent studies show, has the potential to bridge the gap that currently exists between conventional X-ray imaging and electron microscopy. This article covers the evolution of the technology from basic 2D imaging to computed tomography to 3D ptychographic X-ray laminography (PyXL) with zoom. To demonstrate the capabilities of PyXL, a 16-nm FinFET logic IC was mechanically polished to a thickness of 20 µm and several regions were imaged at various levels of resolution.

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop's sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -247dB, and normalized TR and area (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub> ) of -262dB.

A Noise-Canceling Charge Pump for Area Efficient PLL Design

Phase noise of PLLs is one of the critical issues in high-performance transceivers. Especially, in-band noise is troublesome because the phase noise inside a loop bandwidth is hard to be filtered out due to low-pass characteristic of most PLL components. The in-band noise of PLLs is mainly caused by charge-pumps (CPs), so that large-size transistors are used to improve in-band noise of CPs. Due to this trade-off between inband noise and occupied area, a large area is needed for CPs in high-performance transceivers. In this paper, we propose a noise-canceling CP to improve in-band noise. The prototype of the proposed CP embedded in a 28-GHz LC-PLL was fabricated using 16nm FinFET process and 1.2-dB improvement of single sideband (SSB) integrated phase noise is achieved. As the results of in-band noise improvement, occupied area for the CP can be reduced to 22%.

Investigating Heavy-Ion Effects on 14-nm Process FinFETs: Displacement Damage Versus Total Ionizing Dose

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no “rebound” in the ON-state current back to its initial high value; however, the OFF-state current “rebound” was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects.

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation-hardened variants present superior resiliency when either local or global triple modular redundancy (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices

The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.

Implementation of UART Design for RF Modules Using Different FPGA Technologies

This paper is focused on the designing of UART (Universal Asynchronous Receiver Transmitter) for RF based modules, which is a type of serial communication protocol, mainly used for short-distance, low speed and low-cost data transmission between two embedded systems or computer peripherals. These days RF-Microcontroller modules widely uses UART protocol for the interface with other hardware. A reduced FSM (Finite State Machine) UART design has been implemented on different FPGAs. The maximum achievable speed and their corresponding power consumption are calculated using these FPGAs. The proposed design is implemented using Verilog HDL and for simulation purpose, Xilinx ISE 12.1, 14.7, Xilinx Vivado 2018 and Intel Quartus Prime 19.1 are used. The smallest value of maximum power consumption i.e. 20.67mW at 105.47MHz frequency with 180nm technology node is achieved by Intel Max V among all the Intel and Xilinx devices. Furthermore, the maximum achievable frequency i. e. 769.48 Hz has been found in Virtex 4 FPGA device. Xilinx Virtex UltraScale+ devices occupy the minimum area which provides 16-nm FinFET Technology node.

Suppression of Stress-Induced Defects in FinFET by Implantation and STI Co-Optimization

Defects originated from the stress-induced fin dislocation in FinFET have become critical in taller and narrower fin structures at advanced technology nodes that can easily form a leakage path between the source and the drain, leading to direct short failure. In this work, the correlation between the stress-induced defect and device leakage current has been studied using 14-nm FinFET devices with different fin structures. A novel method to detect and quantify the fin dislocation defect has been developed by characterizing the leakage performance, which can be used to evaluate the process effects. The asymmetric stress from shallow trench isolation (STI) oxide film and fin damage by ion implantation are verified as the primary causes through statistical analysis, which have been further co-optimized to achieve a higher yield.

Evidence of Interface Trap Build-Up in Irradiated 14-nm Bulk FinFET Technologies

Total ionizing dose response of 14-nm bulk-Si FinFETs has been studied with a specially designed test chip. The radiation testing shows evidence of interface trap build-up on 14-nm Bulk FinFET technologies. These defects created in the isolation layer give rise to a new radiation-induced leakage path which might lead to a reliability issue in CMOS technologies at or below the 14-nm node. TCAD simulations are performed and an analytical model for TID-induced leakage current is presented to support analysis of the identified TID mechanism. TCAD simulation and analytical model results are consistent with the experimental data.

Total Ionizing Dose Responses of 22-nm FDSOI and 14-nm Bulk FinFET Charge-Trap Transistors

Total-ionizing-dose (TID) effects are investigated for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state for both silicon on insulator (SOI) and bulk devices. To first order, ionizing radiation does not interact strongly with programing-induced charges in the gate dielectric for either device type. Hole trapping in the buried oxide dominates the TID response of the 22-nm FDSOI devices. The 14-nm bulk devices with two fins and total effective fin widths of 150 nm are minimally affected by TID, but the subthreshold leakage of devices with 40 fins and total effective fin widths of 3 μm increases with increasing TID. When devices are programmed or reprogrammed after irradiation, significant increases in subthreshold slope are observed due to the generation of interface traps, border traps, and/or charge lateral nonuniformities.

22nm FINFET Based High Gain Wide Band Differential Amplifier

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs

In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by $4.0\times $ ( $2.7\times $ ) and $1.8\times $ ( $2.1\times $ ) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

DRAM Bandwidth Optimal Perspective Transform Engine

Perspective transform (or Homography) is commonly used algorithms in ADAS and Automated Driving System. Perspective transform is used in multiple use-cases e.g. viewpoint change, fisheye lens distortion correction, chromatic aberration correction, stereo image pair rectification, This algorithm needs high external DRAM memory bandwidth due to inherent scaling, resulting in nonaligned two dimensional memory burst accesses, resulting in large degradation in system performance and latencies. In this paper, we propose a novel perspective transform engine to reduce external memory DRAM bandwidth to alleviate this problem. The proposed solution consists of multiple regions slicing of input video frame with block size tuned for each region. The paper also gives an algorithm for finding optimal region boundaries with corresponding block size tuned for each region. The proposed solution enables average BW reduction of 67% compared to traditional implementation and achieves clock up-to 720 MHz with output pixel throughput of 1 cycle/pixel in 16nm FinFET process node.

A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers

Temperature rising is an unavoidable effect on VLSI and has always been a critical issue in any system-on-chip &#x2013; especially when targeting compute-intensive applications. This effect increases the delay in hardware accelerators, resulting in timing errors due to unsustainable clock frequency, whose impact must be carefully evaluated on design time to measure the performance degradation of the hardware accelerator. Further, a hardware operating at a higher temperature accelerates device aging, which incurs in more timing errors. This issue is usually addressed with the inclusion of timing guardbands that compensate for the deleterious effects of temperature, ensuring the hardware accelerator works within a reliable zone, i.e., without any timing errors caused by temperature effects at runtime. However, guardbands directly result in considerable performance and efficiency losses because the circuit will be clocked at a frequency lower than its full potential. Accelerators on edge devices often dismiss such guardbands to explore the full potential of the designed circuits, posing an enormous design challenge as this approach requires a careful evaluation of the impact of timing errors on the quality of the target applications. Many algorithms, such as in multimedia and machine learning applications, are capable of tolerating hardware errors. Yet, these algorithms have a dynamic behavior (i.e., closed-loop) where a timing error can be propagated, affecting subsequent steps. Measuring the degradation-induced errors in these applications is very challenging given that an accurate gate-level simulation to investigate degradation-induced timing errors needs to be coupled dynamically with a system-level simulator to unveil how induced errors in the underlying hardware ultimately impact the algorithm execution in the hardware accelerator. <i>This is the first work to achieve this goal</i>. State-of-the-art works have studied accelerators under timing-errors when removing (or narrowing) guardbands. However, their approach was suitable <i>only for open-loop hardware accelerators which are entirely agnostic of complex interactions of the algorithms</i>. Unlike prior work, this paper investigates temperature- and aging-induced timing-errors in the joint accelerator-algorithm interactions and their runtime impacts. Our framework investigates aging effects across the different layers starting from transistor physics all the way up to the algorithm layer. The hardware accelerator employed as a case study in this work is the sum of absolute differences (SAD), which is the most compute-intensive accelerator on commercial video encoder for mobile applications. Our results demonstrate the runtime behavior impacts of three advanced block-matching algorithms of the video encoder in a joint operation by a SAD accelerator under timing-errors induced by temperature and aging effects considering a 14nm FinFET technology.

Высокоточный двухступенчатый АЦП с изменяемым диапазоном сравнения с использованием компаратора на основе защелки

Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.

A HIGH EFFICIENCY OPERATIONAL TRANSCONDUCTANCE AMPLIFIER DESIGN WITH CONTROLLABLE BANDWIDTH IN THE 14NM FINFET TECHNOLOGY

Operational transconductance amplifiers are high gain amplifiers with wide bandwidth. The main advantage of those circuits is their capability to drive high resistive and capacitive loads at their outputs. Due to such capability, such circuits consume high power. While in some applications where the current consumption may vary in wide ranges the self-current of those amplifiers may succeed the load current, thus decreasing the efficiency coefficient of the designs. To reduce the intrinsic current consumption without impacting the performance and functionality, a novel method of an operational transconductance amplifier output stage design is proposed in this paper. The programmable output stage, in which the output cascade can operate in two different modes using a digital control signal has been designed. As a result, the parameters of the operational amplifier become more flexible to be tuned and configured after production. The output impedance, amplifier transconductance, bandwidth and other main parameters can be easily controlled based on the system state. If the load at the output enters the power down mode, the impedance of the amplifiers decreases the current and vice versa. The solution has been tested in the modern 14nm FinFet technology and the achieved results have ensured the capability of the proposed solution to be integrated with modern analog integrated circuits.

Impact of NCFET on Neural Network Accelerators

This is the first work to investigate the impact that Negative Capacitance Field-Effect Transistor (NCFET) brings on the efficiency and accuracy of future Neural Networks (NN). NCFET is at the forefront of emerging technologies, especially after it has become compatible with the existing fabrication process of CMOS. Neural Network inference accelerators are becoming ubiquitous in modern SoCs and there is an ever-increasing demand for tighter and tighter throughput constraints and lower energy consumption. To explore the benefits that NCFET brings to NN inference regarding frequency, energy, and accuracy, we investigate different configurations of the multiply-add (MADD) circuit, which is the core computational unit in any NN accelerator. We demonstrate that, compared to the baseline 7nm FinFET technology, its negative capacitance counterpart reduces the energy by 55%, without any frequency reduction. In addition, it enables leveraging higher computational precision, which results to a considerable improvement in the inference accuracy. Importantly, the achieved accuracy improvement comes also together with a significant energy reduction and without any loss in frequency.

Energy- and Quality-Efficient Approximate Multipliers for Neural Network and Image Processing Applications

Approximate computing is a new trend that trades off computational accuracy for lower energy dissipation and design complexity in various applications, where high precision is not a critical need. In this paper, energy- and quality- efficient approximate multipliers based on new approximate compressors are proposed. We use NAND gates for generating the complemented partial products, which reduces the number of transistors. Furthermore, new approximate compressors with different accuracy and performance characteristics are designed. Accordingly, three hybrid approximate multipliers offering different trade-offs between accuracy and hardware efficiency are proposed. The proposed designs are simulated using HSPICE with the 7nm FinFET model as a modern technology. Furthermore, the efficacies of the approximate multipliers in the neural network and image processing applications are evaluated using MATLAB. According to the results, the proposed designs provide far better compromises between the quality and energy metrics in comparison with the previous designs and can be considered as efficient alternatives for the exact multipliers in neural network and image processing applications.