6T SRAM Research Articles

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation

This paper aims to explore the design of a novel highly stable low-energy 10T (SLE10T) SRAM cell for near-threshold operation. The latch core of the proposed design consists of a cross-coupled structure of a tri-state inverter and a standard inverter. The tri-state inverter is switched to the high-impedance mode during a write operation to temporarily float the data node, improving writability. In addition, read stability is equivalent to hold stability due to considering a separate path for read current flow, as well as a built-in read-assist scheme to force the ‘0’ storing node to ground. Leakage and dynamic power consumptions in the designed cell are reduced with the help of single-bitline structure and stacking of transistors. The simulation results in a 7-nm FinFET at a 0.5 V show that the SLE10T improves read stability by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.31\times $ </tex-math></inline-formula> compared to read-disturbance SRAMs and offers the second-highest writability, improvement of at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> . Leakage power dissipation is reduced in the SLE10T by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> . Moreover, it improves read/write energy by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.01\times /1.03\times $ </tex-math></inline-formula> . However, the area of the SLE10T bitcell is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.02~\mu \text{m}^{2}$ </tex-math></inline-formula> , which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.657\times /1.318\times $ </tex-math></inline-formula> larger than the conventional 6T/8T bitcell.

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Design of a stable single sided 11T static random access memory cell with improved critical charge

AbstractRadiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

Tunnel FET and MOSFET Hybrid Integrated 9T SRAM with Data-Aware Write Technique for Ultra-Low Power Applications

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications.

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design

Deep neural network (DNN) has recently attracted tremendous attention in various fields. But the computing operation requirement and the memory bottleneck limit the energy efficiency of hardware implementations. Binary quantization is proposed to relieve the pressure of hardware design. And the Computing-In-Memory (CIM) is regarded as a promising method to resolve the memory wall challenge. However, the binary computing paradigm is mismatched with the CIM scheme, which incurs complex circuits and peripheral to realize binary operation in previous works. To overcome previous issues, this work presents Binary Representation Computation-In-Memory (BR-CIM) with several key features. (1) A lightweight computation unit is realized within the 6T SRAM array to accelerate binary computing and enlarge signal margin; (2) The reconfigurable computing scheme and mapping method support extendable bit precision to satisfy the accuracy requirement of various applications; (3) Simultaneous computing and weight loading is supported by column circuitry, which shortens the data loading latency; Several experiments are conducted to estimate algorithm accuracy, the computing latency, and power consumption. The energy efficiency reaches up to 1280 TOPs/W for binary representation. And the algorithm accuracy achieves 97.82%/76.4% on MNIST/CIFAR-100 dataset.

Single-Ended 8T SRAM cell with high SNM and low power/energy consumption

ABSTRACT This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written ‘1’, enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications.

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture

The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture is proposed to perform energy-efficient IMBC operations. The local bit-line shared pass-gate structure addresses the half select issues with a small area overhead and achieves higher array efficiency by incorporating the bit-interleave architecture. The virtual-VSS write-assist is used in SDP8T SRAM to improve the write-margin yield (μ−3σ) by 48.99%, and multi-VTH technique improves Decoupled Read-Margin (DRM) yield by 5.26% when compared to DP8T SRAM. The Dynamical Reset Word Line (DRWL) scheme is proposed to resolve the sneak current problem and make the proposed IMC architecture more resilient to compute disturbance at non-read decouple paths during IMBC operations. Further, the Reference-based Reconfigurable Sense Amplifier (RRCSA) scheme is proposed to achieve reliable (compute-failure free) sensing for IMBC on four operands simultaneously in a single cycle, normal read, and Binary Content Addressable Memory (BCAM) operations. The 4 Kb SRAM array is implemented in 65-nm CMOS technology to analyze the SDP8T-IMC architecture. The operating frequency of 1190 MHz and average-energy consumption of 18.56 fJ/bit are achieved during IMBC operation at 1V. For BCAM operations, it achieves 0.60 fJ/search/bit energy consumption in the worst case (i.e., all data mismatch) at 1V. Cumulatively, the proposed SDP8T-IMC architecture has the highest figure of merits than the recently reported IMC architecture.

Design and Analysis of SRAM Cell for Smart Application

In today's circuittechnology, power consumption and savings are key concerns. The driving reasonsbehind these innovations are portable devices that require high throughput andlow power dissipation, such as computers, phones, and Personal DigitalAssistants (PDAs). In portable devices, reducing or decreasing IC dissipatedpower through design optimization is a big problem, and restricted batterylifespan places very severe restrictions on overall power usage. In this study SRAMcircuit for smart applications has been investigated using various factors suchas write, read, dynamic, static power with voltage and temperature. The powerconsumption analysis is the most essential criteria for memory design. Becausedata stability is a critical concern, affecting both the read and write operations.The implemented 9T SRAM in this study is more efficient than the other SRAM interms of power usage. When compared with the existing SRAM circuits taken forcomparison of different parameters, the proposed 9T SRAM, circuit uses lessthan 28.2% write power, while it uses about the same for read operation. Thedata retention voltage for both circuits is 0.29 V, which is utilized to storethe data in the circuit. The 32 nm Bulk CMOS process technology from PTM filesis used for designing and analysis.

Analysis of back-gate bias impact on 22 nm FDSOI SRAM cell

The back-gate terminal biasing has been used to improve the SRAM cells’ performance. In this paper, the impact of back-gate bias on the performance of 22 nm FDSOI SRAM 6T cell is analyzed. The cell is fabricated in the regular well and two back-gate terminals are connected to Pwell and Nwell, respectively. The influences of back-gate bias on the cell are studied by the variations of the metrics of leakage current, read current, static noise margin (SNM) and N-curve under the three back-gate bias combinations. Through measurements and HSPICE simulations, the mechanism of the variations of the cell metrics caused by the changes of the back-gate bias is explained by the shift of electrical characteristics of transistors inside the cell.

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications

In this work, we present a 6T SRAM computing-in-memory(CIM) macro in robust charge domain using (1) a local process element with digital-to-analog-converter-less input for eliminating non-linear and variation caused by multi-bit input, supporting XNOR and AND operations, (2) an in-memory 4-bit weight accumulation scheme for multiply-and-accumulate (MAC) operation, to reduce energy cost and achieve area-compact design, (3) a reconfigurable prioritized subranging analog-to-digital-converter for energy saving, supporting a 4-b or 4 2.24-b quantizations for multi-mode operations. The proposed design support AND and XNOR MAC operations. With a layout implementation in 28 nm CMOS process, the 128 kb SRAM CIM macro achieves good computing linearity and variation. The array area efficiency is 76.63%. The average energy efficiency is 175.2 TOPS/W while performing AND mode MAC with 2-b input and 4-b weight, and is 1379.4 TOPS/W in XNOR mode MAC. The behavioral simulation shows a classification accuracy of 85.55% in CIFAR-10. The average accuracy loss is only 1.37% compared with the software baseline.

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

Improved read/write assist mechanism for 10‐transistor static random access memory cell

AbstractThis paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell.

Design of a High Performance 1 Kb SRAM Array Using Proposed Soft Error Hardened 12T SRAM Cell

The shrinking of technology node and supply voltage has a profound effect on various design metrics of the SRAM cell. Available SRAM designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T SRAM cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High-[Formula: see text] transistors in read path to reduce the read power and leakage power. The critical charge of P12T SRAM cell is 9.13% and 15.21% higher than the 8T and 10T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. P12T SRAM cell has 41.61% and 21.4% decrease in read power than 8T and AS10T SRAM cells, respectively, at SS corner for 0.9[Formula: see text]V [Formula: see text]. In P12T SRAM cell, write 1 PDP at worst case corner SS is [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] lower than 8T, AS8T, AS10T, 10T, and 12T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. Monte Carlo simulation has been done to study variability and half-select issue. 1[Formula: see text]Kb bit interleaving SRAM array is designed using P12T SRAM cell and 12T SRAM cell. 1[Formula: see text]Kb SRAM array using P12T SRAM cell has superior write PDP than 12T SRAM cell. Postlayout simulation has been carried out on all the SRAM cells to estimate different metrics in 45[Formula: see text]nm technology using the Cadence Virtuoso.

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of <inline-formula> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2^N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm², respectively.

Enabling In-Memory Computations in Non-Volatile SRAM Designs

The rapid growth in development of neural networks has necessitated the requirement of large capacity on-chip SRAM’s for Machine Learning accelerators. This has resulted in SRAM’s occupying significant portion of the die area. Furthermore, due to increased short channel effects in advanced CMOS technology nodes, the Vt of the transistors are increased to reduce the leakage power effectively. Vt increase results in direct increase in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> (minimum operating voltage) of the device. The conventional 6T SRAM with the use of RRAM(R) to store the bitcell storage node values and PTM(S) as a selector device (6T-2R-2S) can help in decoupling V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and Vt requirement with minimum area overhead. Functionalities of 6T-2R-2S bitcell are investigated to present a 2T-2R-2S mode and SRAM-RRAM hybrid mode of operation, further utilized in performing Compute in Memory(CIM). The above functionalities can be presented in a 8T2R bitcell, that makes use of transistor in place of PTM. 2T-2R-2S/2T-2R mode is a fully non-differential mode of operation, leveraging only the NVM portion of the bitcell. Furthermore, SRAM-RRAM hybrid mode is proposed making use of the SRAM read port transistors to perform read operation of the data stored on the RRAM, during standby mode. The architecture study of set-associative cache made of 6T-2R-2S array is also presented. The 2T-2R-2S/2T-2R mode coupled with SRAM-only mode can be efficiently used to perform CIM for dot product and XNOR computation with co-locating the weights and activations stored onto the same bitcell. System level study highlighting energy efficiency and speedup along with the proposed CIM architecture’s analysis on CIFAR-10 dataset is presented. Design sensitivity analysis with respect to PTM and RRAM parameters is discussed for both the bitcells.

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices

Compute-in Memory (CIM) has been a promising candidate to perform the energy-efficient multiply-and-accumulate (MAC) operations of the modern Artificial Intelligence (AI) edge devices. This work proposes a multi-bit precision (4b input, 4b weight, and 4b output) 128 × 128 SRAM CIM architecture. The 4b input is implemented using the voltage-scaling and charge-sharing-based scheme. To achieve efficient computation with improved linearity, a novel AND-logic-based 8T SRAM cell (AND8T) is proposed. To address the non-idealities of analog voltage or current-based operations, the proposed AND8T employs the charge-domain-based computation by overlaying a metal-oxide-metal capacitor (MOM cap) with no area overhead. The proposed AND8T mitigates the linearity issue of MAC operations which is highly desirable for the reliable operation of complex neural networks (CNNs). The proposed 16Kb macro asserts 128 inputs in parallel and processes a 128 4b dot-product in a single cycle for the array column (a single neuron). The macro can also be reconfigured for the 64 or 32 4b parallel inputs based on the need of CNN models. The AND8T SRAM macro is fabricated in a 65nm node and achieves an energy efficiency of 301.08 TOPS/W for 16 parallel neurons output, with 128 4b MAC operations at 10MHz clock frequency and 1V supply. The implemented macro supports up to 100MHz of clock frequency and occupies 0.124mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area while achieving the 96.05% and 87% classification accuracy for MNIST and CIFAR-10 datasets.

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary assistance circuits or alternative bitcell topologies, but they lead to substantial overheads of the access speed or array density. In this article, we propose a novel 8T compute SRAM (CSRAM) for reliable and high-speed in-memory searching and compound logic-in-memory computations. Our 8T CSRAM features a pair of pMOS access transistors and split-WLs dedicated to the compute access. A thorough circuit-level analysis reveals that the pMOS-based compute access port is essential for significantly mitigating the read disturbance. Moreover, we propose an elevated precharge voltage scheme and a low-skewed inverter-based sensing amplifier to improve the sensing speed. We have validated the proposed 8T CSRAM design in a 16 Kb array with a 28-nm CMOS technology. Compared to the state-of-the-art 8 T CSRAM, results show that our design is not only reliable but also 3.1 times faster, with a maximum operating frequency upping to 2.44 GHz.

Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications

Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications