10-bit Analog-to-digital Converter Research Articles

Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

This paper presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multiply-and-accumulate (MAC). The columnsensing dual-phase 6b successive-approximation-register (SAR) analog-to-digital-converter (ADC) maximizes the through-put with minimized pitch. The proposed CIM occupies an active area of 0.0155mm2 and consumes 4.36mW with an average energy efficiency of 25.8TOPS/W. The measured performance achieves the highest normalized throughput with an end-to-end inference accuracy comparable to FP32 with less than a 0.11% drop.

Quantization error for weak RF simultaneous signal estimation

In a congested signal environment, it is difficult to obtain estimates of weak RF signal parameters. Determining signal parameter estimates in real time is a challenge for electronic warfare receivers that aim to receive multiple simultaneous signals. Prior work provided estimates of weak signal parameters (weak signal frequency and weak signal amplitude) without taking into account any error introduced by analog-to-digital converters that are inherently part of digital signal processing systems. In order to obtain realistic estimates, we need to take error introduced by an ADC into account. The primary aim of this paper is to quantify error introduced by a single ideal ADC as a function of angle. This paper presents a method to estimate angle resolution and quantization levels in N-bit analog-to-digital converters (ADCs) for use in a weak radiofrequency (RF) simultaneous signal estimation process. The paper quantifies the error in the angle quantization of an N-bit ADC for an input complex signal that is the instantaneous frequency obtained for the situation in which there are two simultaneous signals (with one strong signal and one weak signal) in a weak RF simultaneous signal estimation process. The presented method describes the process to determine the angle quantization range, angle quantization uncertainty, and angle quantization error. This approach has potential applications in electronic warfare (EW) systems. The approach also has potential for assessing ADC performance for measurements that approach the quantum limit. Results are presented for 1-bit, 2-bit, 3-bit, and 10-bit ADCs.

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems.

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor's operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

Dynamic Predictive Sampling Analog to Digital Converter for Sparse Signal Sensing

This paper presents a dynamic predictive sampling (DPS) based analog-to-digital converter (ADC) that provides a non-uniform sampling of input analog continuous-time signals. The processing unit generates a dynamic prediction of the input signal using two prior-quantized samplings to compute digital values of an upper threshold and a lower threshold. The digital threshold values are converted to analog thresholds to form a tracking window. A dynamic comparator compares the input analog signal with the tracking window to determine if the prediction is successful. A counter records timestamps between the unsuccessful predictions, which are the selected sampling points for quantization. No quantization is performed for successfully predicted sampling points so that the data throughput and power can be saved. The proposed circuits were designed as a 10-bit ADC using 0.18 micro CMOS process sampling at 1 kHz. The results show that the proposed system can achieve a data compression factor of 6.17 and a power saving factor of 31% compared to a Nyquist rate SAR ADC for ECG monitoring.

Accurate Sneak-Path-Controlled Readout for a Cross-Point Resistive Sensor Array

A readout method of measuring resistances from a sensor array is proposed. As opposed to the conventional method of feedback readout, in which the crosstalk is suppressed by an op-amp, the sneak paths are controlled by switches, and a matrix equation of the circuit is derived from measured voltage. Thus, the scanning speed and power consumption of an interface circuit are not inherently deteriorated by the op-amp. The main factors affecting readout accuracy are parasitic resistance of the analog switch and quantized error of the analog-to-digital converters (ADCs). Therefore, calibration of switch resistance is also proposed to maintain readout accuracy by additional ADCs. To evaluate the proposed readout system, “sneak-path-controlled readout” (SPCR) and “accurate sneak-path-controlled readout” (ASPCR) are implemented. To verify the accuracy of the proposed readout method, the interface circuit and the calibration of switch resistance were simulated by MATLAB. The target array size was 32×32, and the sensor resistances were distributed in the same manner as real sensors. Since readout performance is also affected by the pattern of resistances, several patterns of resistance were prepared, and their results were compared. The results of the simulations show that SPCR using a 16-bit ADC can read normally distributed sensors with readout error of 0.05%. Moreover, ASPCR can handle a wider resistance distribution, and its readout error was less than 0.3% with a resistance pattern in which resistance ranges from 1.71 kΩ to 217 kΩ.

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR &gt; 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply.

An ASIC for Gripper Finger Haptic Force Feedback in Minimally Invasive Surgery.

In this article, we present an application specific integrated circuit (ASIC) for gripper finger haptic force feedback in minimally invasive surgery (MIS). It consists of a driving current source, a sensing channel, a digital to analog converter (DAC), a power management unit (PMU), a clock generator and a digital control unit (DCU). The driving current source features a 6-bit DAC to provide a temperature-insensitive current from 0.27 mA to 1.15 mA for the sensor array. The sensing channel contains a programmable instrumentation amplifier (PIA), a low-pass filter (LPF), an incremental analog-to-digital converter (ADC) with its input buffer (BUF). The gain of the sensing channel ranges from 2.76 to 140. The DAC generates a tunable reference voltage to compensate possible sensor array offset. The input referred noise of the sensing channel is around 3.6 μVrms at a sampling rate of 850S/s. A custom 2-wire communication protocol is implemented to support two chips on gripper fingers operating in parallel with low latency, ensuring real-time surgical condition estimation for surgeons. Manufactured in the TSMC 180nm CMOS technology, this chip occupies only 1.37 mm2 core area, and the entire system requires only 4 wires (including power / ground) to operate. Combined with its high accuracy, low latency, and high integration level, this work allows real-time, high-performance haptic force feedback with compact system size, particularly suitable for MIS applications.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

A subranging nonuniform sampling memristive neural network-based analog-to-digital converter

This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the memristive neural network calibration and utilizes a trainable memristor weight to adapt to device mismatch and increase accuracy. Rather than conventional binary searching, we adopt quaternary searching in the ADC to realize subranging architecture’s coarse and fine bits determination. A level-crossing nonuniform sampling (NUS) is introduced to the proposed ADC to enhance the ENOB under the same resolutions, power, and area consumption. Area and power consumption are reduced through circuit sharing between different stages of bit determination. The proposed 4-bit ADC achieves a highest ENOB of 5.96 and 5.6 at cut-off frequency (128 MHz) with power consumption of 0.515 mW and a figure of merit (FoM) of 82.95 fJ/conv.

A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

To address the problem of low trigger accuracy during trigger resampling and variable sampling rate trigger resampling using a fixed sampling rate analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve accuracy, based on a digital trigger. After behavior simulation verification and actual field programmable gate array (FPGA) test verification, the data collected by two 3GSps 12-bit ADCs were subjected to 8-times sinc interpolation followed by 16-times linear interpolation processing, after which the original trigger resampling accuracy was increased by 128 times and the sampling rate could be realized to vary between 100 MHz and 1 GHz. A signal–noise ratio (SNR) of 46.80 dBFS, a spurious free dynamic range (SFDR) of 45.91 dB, and an effective number of bits (ENOB) of 7.48 bits were obtained by direct trigger resampling without algorithm processing in the behavior simulation. Meanwhile, an SNR of 58.98 dBFS, an SFDR of 60.96 dB, and an ENOB of 9.42 bits were obtained by trigger resampling after algorithm processing. Due to the influence of analog link signal loss and signal interference on the development board, an SNR, SFDR and ENOB of 51.97 dBFS, 61.26 dB, and 8.32 bits, respectively, were obtained from the trigger resampling in the FPGA test. The experimental results show that the algorithm has not only improved the triggering accuracy but has also improved the SNR, SFDR, and ENOB parameters.

Virtual-carrier-assisted 12 Gb/s 64QAM millimeter-wave signal transmission at 30 GHz using a 4-bit digital-to-analog converter.

We propose and experimentally demonstrate a radio-frequency digital resolution enhancer (RF-DRE) to mitigate the quantization noise of the RF signal induced by the low-resolution digital-to-analog converter (DAC) in the virtual-carrier-assisted millimeter-wave (mm-wave) signal transmission system. By introducing a bandpass filter (BPF) as the reference for the RF-DRE algorithm, we can design the quantization noise and shape its spectrum inversely to the bandpass filter. By these means, the quantization noise in the target RF frequency range can be effectively mitigated. In the simulation, the bit error rate (BER) of a 4-bit DAC-quantized 16 Gb/s 256QAM signal at 30 GHz is improved from 3.36e-2 to 7.43e-3 by using the RF-DRE. In our experiment, 30 GHz virtual-carrier-assisted mm-wave transmission of 12 Gb/s 64QAM signals over 25 km of standard signal mode fiber (SSMF) is realized. By using the RF-DRE, the BER of a 4-bit DAC-quantized signal can be improved from 6.88e-3 to 1.49e-3, and a 5-bit DAC exhibits a similar performance to an 8-bit DAC without the RF-DRE. Therefore, low-resolution and low-cost DACs can be used for mm-wave signal generation with the help of the proposed RF-DRE.

A column-parallel 1-bit ADC with threshold offset reduction technique for single-bit quanta image sensor

This paper presents a column-parallel 1-bit analog-to-digital converter (ADC) with threshold offset reduction technique, which aims to reduce the bit error rate (BER) of single-bit quanta image sensor (QIS). The fixed offset of the differential charge transfer amplifier (DCTA) and the fixed compensation offset of the calibrated dynamic latch (CD-latch) comparator are eliminated by two coupling capacitors. Additionally, an improved 3-stage DCTA with low gain error is designed to further suppress the fixed residual offset of the CD-latch. The proposed circuit is implemented by a 110 nm CMOS process. Post-simulation results show that the proposed 1-bit ADC achieves a threshold offset of 32.6 μV at 4 MSa/s sampling rate and 500 μV quantization threshold. Compared with the conventional structure, the random noise of the proposed 1-bit ADC remains almost unaltered. Meanwhile, its threshold offset is lowered by 153.6 μV, making the model BER and circuit BER of the column-level circuit reduce from 2.42% to 0.21% and 2.29%–0.26%, respectively.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A VCO-Based 2nd-Order Δ2–ΔΣ Modulator for Small-Size High Energy-Efficient Current Sensing Front-End

In this letter, a 2nd-order 2 -Σ modulator consisting of a voltage-controlled-oscillator-based quantizer (VCOQ) and a current digital-to-analog converter (DAC) with a pulse width modulator (PWM) is presented for the precise acquisition of a wide range photocurrent in an area-and energy-efficient form factor. The proposed 2-modulation realized by the 2nd-order infinite impulse response (IIR) filter on the feedback significantly attenuates the magnitude of input signals, enhancing the DR and linearity. Moreover, an additional differentiator followed by the VCOQ features the negative feedback loop in the 2nd-order Σ modulator, improving noise shaping with no additional current DAC noise. In addition, a 1-bit PWM current DAC substituting the multi-bit current DAC is devised to mitigate the noise from the current DAC, realizing the high resolution of 1 pA with 500 Hz bandwidth. The prototype chip fabricated in a 110-nm CMOS occupies 0.0308 mm2 and achieves Walden FoM of 4.15 pJ/conv.