10-bit Analog-to-digital Converter Research Articles

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

A Calibration Scheme for a 800-Ms/s 14 Bit Pipelined ADC in 28-nm CMOS

Abstract A calibration scheme is proposed to compensate linear and nonlinear errors including offset, cap mismatch, second- and higher-order harmonics and memory induced errors in pipelined analog-to-digital converters (ADCs). The alternating minimization (AM) algorithm is proposed to accurately estimate the coefficients of the errors. As an accurate input value is hardly acquired in practical measurements, instead, the proposed scheme estimates the input and the error coefficients jointly. Once the error coefficient was calculated, it will be recorded in a lookup table (LUT). The scheme has been demonstrated in a 800-Ms/s 14-bit pipelined ADC fabricated in a 28nm CMOS process, which features a signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) improvement of 2.49 dB and 11.49 dB at 800-Ms/s.

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

This paper presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multiply-and-accumulate (MAC). The columnsensing dual-phase 6b successive-approximation-register (SAR) analog-to-digital-converter (ADC) maximizes the through-put with minimized pitch. The proposed CIM occupies an active area of 0.0155mm2 and consumes 4.36mW with an average energy efficiency of 25.8TOPS/W. The measured performance achieves the highest normalized throughput with an end-to-end inference accuracy comparable to FP32 with less than a 0.11% drop.

Quantization error for weak RF simultaneous signal estimation

In a congested signal environment, it is difficult to obtain estimates of weak RF signal parameters. Determining signal parameter estimates in real time is a challenge for electronic warfare receivers that aim to receive multiple simultaneous signals. Prior work provided estimates of weak signal parameters (weak signal frequency and weak signal amplitude) without taking into account any error introduced by analog-to-digital converters that are inherently part of digital signal processing systems. In order to obtain realistic estimates, we need to take error introduced by an ADC into account. The primary aim of this paper is to quantify error introduced by a single ideal ADC as a function of angle. This paper presents a method to estimate angle resolution and quantization levels in N-bit analog-to-digital converters (ADCs) for use in a weak radiofrequency (RF) simultaneous signal estimation process. The paper quantifies the error in the angle quantization of an N-bit ADC for an input complex signal that is the instantaneous frequency obtained for the situation in which there are two simultaneous signals (with one strong signal and one weak signal) in a weak RF simultaneous signal estimation process. The presented method describes the process to determine the angle quantization range, angle quantization uncertainty, and angle quantization error. This approach has potential applications in electronic warfare (EW) systems. The approach also has potential for assessing ADC performance for measurements that approach the quantum limit. Results are presented for 1-bit, 2-bit, 3-bit, and 10-bit ADCs.

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems.

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor's operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

Dynamic Predictive Sampling Analog to Digital Converter for Sparse Signal Sensing

This paper presents a dynamic predictive sampling (DPS) based analog-to-digital converter (ADC) that provides a non-uniform sampling of input analog continuous-time signals. The processing unit generates a dynamic prediction of the input signal using two prior-quantized samplings to compute digital values of an upper threshold and a lower threshold. The digital threshold values are converted to analog thresholds to form a tracking window. A dynamic comparator compares the input analog signal with the tracking window to determine if the prediction is successful. A counter records timestamps between the unsuccessful predictions, which are the selected sampling points for quantization. No quantization is performed for successfully predicted sampling points so that the data throughput and power can be saved. The proposed circuits were designed as a 10-bit ADC using 0.18 micro CMOS process sampling at 1 kHz. The results show that the proposed system can achieve a data compression factor of 6.17 and a power saving factor of 31% compared to a Nyquist rate SAR ADC for ECG monitoring.

Accurate Sneak-Path-Controlled Readout for a Cross-Point Resistive Sensor Array

A readout method of measuring resistances from a sensor array is proposed. As opposed to the conventional method of feedback readout, in which the crosstalk is suppressed by an op-amp, the sneak paths are controlled by switches, and a matrix equation of the circuit is derived from measured voltage. Thus, the scanning speed and power consumption of an interface circuit are not inherently deteriorated by the op-amp. The main factors affecting readout accuracy are parasitic resistance of the analog switch and quantized error of the analog-to-digital converters (ADCs). Therefore, calibration of switch resistance is also proposed to maintain readout accuracy by additional ADCs. To evaluate the proposed readout system, “sneak-path-controlled readout” (SPCR) and “accurate sneak-path-controlled readout” (ASPCR) are implemented. To verify the accuracy of the proposed readout method, the interface circuit and the calibration of switch resistance were simulated by MATLAB. The target array size was 32×32, and the sensor resistances were distributed in the same manner as real sensors. Since readout performance is also affected by the pattern of resistances, several patterns of resistance were prepared, and their results were compared. The results of the simulations show that SPCR using a 16-bit ADC can read normally distributed sensors with readout error of 0.05%. Moreover, ASPCR can handle a wider resistance distribution, and its readout error was less than 0.3% with a resistance pattern in which resistance ranges from 1.71 kΩ to 217 kΩ.

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR &gt; 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply.

An ASIC for Gripper Finger Haptic Force Feedback in Minimally Invasive Surgery.

In this article, we present an application specific integrated circuit (ASIC) for gripper finger haptic force feedback in minimally invasive surgery (MIS). It consists of a driving current source, a sensing channel, a digital to analog converter (DAC), a power management unit (PMU), a clock generator and a digital control unit (DCU). The driving current source features a 6-bit DAC to provide a temperature-insensitive current from 0.27 mA to 1.15 mA for the sensor array. The sensing channel contains a programmable instrumentation amplifier (PIA), a low-pass filter (LPF), an incremental analog-to-digital converter (ADC) with its input buffer (BUF). The gain of the sensing channel ranges from 2.76 to 140. The DAC generates a tunable reference voltage to compensate possible sensor array offset. The input referred noise of the sensing channel is around 3.6 μVrms at a sampling rate of 850S/s. A custom 2-wire communication protocol is implemented to support two chips on gripper fingers operating in parallel with low latency, ensuring real-time surgical condition estimation for surgeons. Manufactured in the TSMC 180nm CMOS technology, this chip occupies only 1.37 mm2 core area, and the entire system requires only 4 wires (including power / ground) to operate. Combined with its high accuracy, low latency, and high integration level, this work allows real-time, high-performance haptic force feedback with compact system size, particularly suitable for MIS applications.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.