This study presents a comprehensive approach to fine-tuning Cesium Lead Chloride Perovskite Field-Effect Transistors (CsPbCl3-FETs) for sensing applications by bridging numerical modeling with experimental validation. By combining finite element methods in COMSOL Multiphysics for optimization, we tailored FET parameters such as oxide and perovskite thin film thickness. The fabricated FET, with a 200 nm semiconductor layer and 30 nm oxide thickness, was strategically chosen to operate in a non-depletion mode, maximizing mobility while minimizing power consumption. Experimental results closely aligned with numerical simulations, showcasing a threshold voltage of 0.50 V±0.07 V and an impressive on/off current ratio of 1.50 x 104 ± 0.3 x 104. Notably, the perovskite FET exhibited remarkable carrier mobility in saturation mode, reaching 5.40 cm2/V-s ± 0.8 cm2/V-s, outperforming other attempts in the literature. This work underscores the potential of CsPbCl3 FETs for high-performance sensing applications, offering insights into optimizing device parameters for enhanced functionality and efficiency.

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb2+ and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.

In this paper we present measurement results of hot-carrier-induced degradation of NPT-IGBT under the condition of voltage applied on its collector.The effect of hot carriers on NPT-IGBT is investigated in three ways: stress test measurement according to the gate voltage under the voltage of 400 V applied, TCAD (Tsuprem4 and MEDICI) simulation and electric charge pumping test measurement. The experimental results confirm that the proposed structure of NPT-IGBT has sustainable characteristics and enables the hot-carrier-induced degradation to be effectively optimized in order to guarantee the stability of the device.

The AlGaN/GaN high electron mobility transistors (HEMTs) with T-gate that suitable for high frequency applications were fabricated. A novel method to extract the bias-dependent source and drain parasitic series resistances (Rs and Rd) of AlGaN/GaN HEMTs is proposed. By analyzing the distributed capacitance and current generator network in the velocity saturated regions of the AlGaN/GaN HEMTs, a new restriction relationship between small-signal equivalent circuit elements is found. The Rs and Rd can be determined under active bias through wideband S-parameter measurements, which can better reflect the physical mechanism of AlGaN/GaN HEMTs under normal operation. The S-parameters and extrinsic transconductance calculated based the small-signal equivalent circuit element values extracted by the method proposed in this paper are very consistent with the experimental values, which reflects the accuracy of this element extraction method. In this paper, the physical mechanism that causes Rs and Rd to vary with bias voltage is also studied. This study has a deeper insight into the bias-dependence of Rs and Rd, which modifies the understanding for physical mechanisms of AlGaN/GaN HEMTs. The research results provide new ideas for establishing small-signal equivalent circuit models containing more physical effects and is of great significance to GaN-based integrated circuit design.

A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and Lg of 10 μm shows enhanced electrical performance such as maximum drain current (ID,max) of 57 mA/mm, maximum transconductance (gm,max) of 11 mS/mm, and field-effect mobility (μFE) of 59 cm2/V·s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance.

This paper presents a hybrid model for TiO2-based memristors, integrating the dopant drift mechanism with the Schottky barrier theory. We introduce the movement of oxygen vacancies as a dynamic variable to modulate changes in memristors. Furthermore, the variation of the dominate mechanism of the TiO2 memristors under different operating conditions is studied, which is related to the position of the internal oxygen vacancy. The proposed model accurately captures the rectification linearity, and effectively elucidates the dominant current mechanisms manifested in six distinct regions of the I-V curves. Our model exhibits better predication with reduced errors when applied to Pt/TiO2/Pt memristors. The proposed model can well describe the dual-mechanism memristor phenomenon, and provides a reference for the subsequent study of multi-mechanism behavior in memristors.

The large numbers of high-energy carriers that occur in semiconductor devices under semi-on state conditions can cause significant device degradation. The effects of different stresses on the electrical and trapping characteristics of GaN-based high-electron-mobility transistors (HEMTs) are investigated. Test results for GaN HEMTs under semi-on state conditions show that the electrical characteristics of these devices degrade to a certain extent after they are subjected to electrical pulse stress cycles with different drain voltage, frequencies, and duty cycles; a degree of degradation also occurs in the electrical characteristics of the devices when they are subjected to direct current electrical stresses. After electrical stress is applied, the absolute amplitude of the traps in the device increases, thus indicating an increase in the trap density. The results show that voltage is the main driver for device damage, with the current playing an accelerating role through its effects on device temperature or by supplying hot electrons; therefore, the drain voltage has the most significant effect on device degradation, which is mainly due to channel high-energy hot electron injection.

The metal and two-dimension (2D) semiconductor contact interfaces have a more considerable contact resistance hindering carrier injection, which makes the performance of 2D semiconductor devices less than the theory. The contact properties of Ni, Au, and Mo with MoS2 are simulated by the first-principles method. The interface dipole caused by the interface charge redistribution changes the work function difference at the metal-MoS2 interface, so the interface charge redistribution is one of the important factors for correctly evaluating the contact properties. Due to the metal-induced gap states (MIGS) at metal-monolayer (ML) MoS2 interfaces, the Fermi level is strongly pinned to fixed energy, and the Schottky barrier height (SBH) cannot be regulated efficiently by the metal work function. Although the work function of Au is bigger than Ni, the Fermi level of Au is pinned at a higher position. In the meantime, the bandgap of MoS2 narrows and metallization occurs due to the larger MIGS. In the Mo-MoS2 interface, the Fermi level is pinned near the conduction band minimum of MoS2. The contact resistances (Rc) of the three structures are tested by the Circular Transfer Length Method (CTLM), which is consistent with the prediction of the simulation. The Mo-MoS2 has the smallest Rc. The results indicate that contact resistance of 2D semiconductors cannot be simply predicted by soled work functions or Fermi level pinning, but is determined by several factors.

In this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as 14nm technology FinFET and 24nm technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (Ioff), on-current (Ion), threshold voltage (Vth), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device.