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Abstract
HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {dd}}$ </tex-math></inline-formula> /2 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {dd}}$ </tex-math></inline-formula> /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead.
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