Abstract
Abstract Low power and high speed devices are the future transistor technology. The low power and higher the wield of Strained Channels with functionality booster becomes more significance with the device scaling in the device modeling. Tunnel FET (TFET) is the cynosure device in the present and feature transistor technology. This paper evinced the recent past of different gate structural of TFETs particularly, subsequently made few suggestions on the development of new TFET structure. Young’s parabolic approximation 3D analytical method is unveiled to develop TEFT. This proposed model may have least sub-threshold slope, drive current improvement and reduce the ambipolar leakage current when compare with the other existing TFET gate structures. Sentaurus TCAD simulator tool used for the device modeling and characterization.
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