Verifying performance of PCI express in a system for multi giga byte per second data transmission

Abstract

This paper describes the performance verification methodology for a interconnect which was developed for a complex system on chips (SOC) containing multiple intellectual properties (IP). As SOC's are more advanced these days, there is a need for an interconnect to serve as center for communication for various IP cores within the SOC. Verifying the functionality and performance of SOC interconnects can be an important task. There will be existence of different protocols, different types of transactions, and multi-layered topology in a SOC. A more comprehensive approach using tools and technologies can simplify the process of verifying the functionality and performance of SOC interconnects. The major objective of the project is performance verification of SOC on a dedicated channel between peripheral component interconnect express (PCI-e) end point and memory using performance models. With advantages like fast speed, low power consumption and good protocol efficiency, PCI-e is considered as a competent candidate for system interconnects. The bottleneck of these systems mostly lies in the data transmission link between the input-output system and the host system. To address this problem, we are using applying request traffic on data link i.e. from PCI-e to memory, and measured the performance of a data transmission between PCI-e and core of the SOC. Bandwidth is measured at bottleneck for different PCI-e generations (Generation 1, Generation 2, Generation 3), different lane configurations and payloads. Bandwidth obtained is being compared with theoretical peak bandwidth calculated.