Repository of arbitration cores (ROAC) for scheduling in various multi-processor SOCs

Abstract

Increasing demand of multiple functions in a single device or with smaller area leads to more market for devices with System on Chip (SOC). An SOC have multiple Intellectual Properties (IPs) such as Processors, memory, peripherals etcetera on a single chip. These IPs need to have an efficient bus architecture for the communication purpose which further decides the device performance. The most used bus architectures like AMBA AHB, AMBA ASB, AMBA AXI, PCI etcetera uses arbitration algorithms to deal with the data traffic issues between these IP cores on a single silicon chip. Therefore a repository of various resizable and reusable arbitration methods has been presented in this paper for scheduling purposes in various multiprocessor system on chips (SOCs). The library consists of five arbitration methods such as Dynamic first in first out (DFIFO), Circular queue, Priority, Dynamic last in first out (DLIFO), and multilevel queue, which are compatible with various Hardware Design and Verification Languages (HDVL). The repository proposed is independent of platform, target, vendor and tool chain. It is generic and helps in fast implementation of IP cores. Every arbitration method in this library can be molded according to the specification needed or required for the SOC. The results are comparatively observed on the basis of area, power and delay. As the results shows that the proposed Circular Queue Scheduling technique is more proficient arbitration method as it take very less time delay and power. It proves to be a starvation free method. The area utilized by Circular queue Scheduler on Spartan 6 XC6SLX45 FPGA is also minimum amongst the other arbitration techniques presented in this repository.